AD9106BCPZRL7 View Datasheet(PDF) - Analog Devices

Part Name

Description

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AD9106BCPZRL7

Quad, Low Power, 12-Bit, 180 MSPS, Digital-toAnalog Converter and Waveform Generator

Analog Devices 

AD9106

THEORY OF OPERATION

Data Sheet

TRIGGER

AD9106

START ADDR

START DLY

STOP ADDR

DAC1 TO DAC2

TIMERS + STATE MACHINES

ADDRESS 1, 2

DPRAM

ADDRESS 3, 4

DAC3 TO DAC4

TIMERS + STATE MACHINES

START DLY

START ADDR

STOP ADDR

1.8V

LDOs

SPI

INTERFACE

10kΩ

1V

RSET2

16kΩ

GAIN1 OFFSET1

DAC1

IREF

100µA

GAIN2 OFFSET2

DAC2

GAIN3 OFFSET3

DAC3

BAND

GAP

GAIN4 OFFSET4

DAC4

PHASE1

PHASE2

TUNING WORD

DAC CLOCK

DDS

DDS1

DDS2

DDS3

DDS4

1.8V

LDO

PHASE3

PHASE4

CLOCK

DIST

RSET1

16kΩ

AGND

RSET3

16kΩ

DAC1

DAC2

DAC3

DAC4

IOUTP1

IOUTN1

AVDD1

IOUTP2

IOUTN2

IOUTP3

IOUTN3

AVDD2

IOUTP4

IOUTN4

RSET4

16kΩ

Figure 31. AD9106 Block Diagram

Figure 31 is a block diagram of the AD9106. The AD9106 has

be connected to DVDD, with the on-chip LDOs disabled. All

four 12-bit current output DACs.

three supplies are provided externally in this case. This also

The DACs use a single common voltage reference. An on-chip

applies to CLKVDD and CLDO if CLKVDD = 1.8 V.

band gap reference is provided. Optionally, an off-chip voltage

Digital signals input to the four DACs are generated by on-chip

reference may be used. Full-scale DAC output current, also

digital waveform generation resources. Twelve-bit samples are

known as gain, is governed by the current, IREF. IREF is the

input to each DAC at the CLKP/CLKN sample rate from a

current that flows through each IREF resistor. Each DAC has its

dedicated digital data path. Each DAC’s data path includes gain

own IREF set resistor. These resistors may be on or off chip at

and offset corrections and a digital waveform source selection

the discretion of the user. When on-chip RSET resistors are in

multiplexer. Waveform sources are SRAM, direct digital

use DAC gain accuracy can be improved by employing the

synthesizer (DDS), DDS output amplitude modulated by SRAM

product’s built in automatic gain calibration capability. Auto-

data, a sawtooth generator, dc constant, and a pseudo-random

matic calibration may be used with the on-chip reference or

sequence generator. The waveforms output by the source

an external REFIO voltage. A procedure for automatic gain

selection multiplexer have programmable pattern character-

calibration is presented in this section.

istics. The waveforms can be set up to be continuous,

The power supply rails for the AD9106 are AVDD for analog

circuits, CLKVDD/CLDO for clock input receiver and

DVDD/DLDO1/DLDO2 for digital I/O and for the on-chip

continuous pulsed (fixed pattern period and start delay within

each pattern period), or finite pulsed (a set number of pattern

periods are output, then the pattern stops).

digital data path. AVDD, DVDD, and CLKVDD can range from

Pulsed waveforms (finite or continuous) have a programmed

1.8 V to 3.3 V nominal. DLDO1, DLDO2, and CLDO run at

pattern period and start delay. The waveform is present in each

1.8 V. If DVDD = 1.8 V, then DLDO1 and DLDO2 should both

Rev. A | Page 20 of 48

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