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AD9106-EBZ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD9106-EBZ Quad, Low Power, 12-Bit, 180 MSPS, Digital-toAnalog Converter and Waveform Generator ADI
Analog Devices ADI
AD9106-EBZ Datasheet PDF : 48 Pages
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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9106
SCLK 1
SDIO 2
DGND 3
DLDO2 4
DVDD 5
DLDO1 6
SDO/SDI2/DOUT 7
CS 8
AD9106
TOP VIEW
(Not to Scale)
24 FSADJ2/CAL_SENSE
23 CLKVDD
22 CLDO
21 CLKP
20 CLKN
19 CLKGND
18 REFIO
17 FSADJ4
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic
Description
1
SCLK
SPI Clock Input.
2
SDIO
SPI Data Input/Output. Primary bidirectional data line for the SPI port.
3
DGND
Digital Ground.
4
DLDO2
1.8 V Internal Digital LDO1 Output. When the internal digital LDO1 is enabled, this pin should be bypassed
with a 0.1 µF capacitor.
5
DVDD
3.3 V External Digital Power Supply. DVDD defines the level of the digital interface of the AD9106 (SPI
interface).
6
DLDO1
1.8 V Internal Digital LDO2 Outputs. When the internal digital LDO2 is enabled, this pin should be bypassed
with a 0.1 µFcapacitor.
7
SDO/SDI2/DOUT Digital I/O Pin.
In 4-wire SPI mode, this pin outputs the data from the SPI.
In double SPI mode, this pin is a second data input line, SDI2, for the SPI port used to write to the SRAM.
In data output mode, this terminal is a programmable pulse output.
8
CSE
A
SPI Port Chip Select, Active Low.
9
RESETE
A
Active Low Reset Pin. Resets registers to their default values.
10
IOUTP4
DAC4 Current Output, Positive Side.
11
IOUTN4
DAC4 Current Output, Negative Side.
12
AVDD2
1.8 V to 3.3 V Power Supply Input for DAC3 and DAC4.
13
IOUTN3
DAC3 Current Output, Negative Side.
14
IOUTP3
DAC3 Current Output, Positive Side.
15
AGND
Analog Ground.
16
FSADJ3
External Full-Scale Current Output Adjust for DAC3.
17
FSADJ4
External Full-Scale Current Output Adjust for DAC4.
18
REFIO
DAC Voltage Reference Input/Output.
19
CLKGND
Clock Ground.
20
CLKN
Clock Input, Negative Side.
21
CLKP
Clock Input, Positive Side.
22
CLDO
Clock Power Supply Output (Internal Regulator in Use), Clock Power Supply Input (Internal Regulator
Bypassed).
23
CLKVDD
Clock Power Supply Input.
24
FSADJ2/CAL_SENSE External Full-Scale Current Output Adjust for DAC2 or Sense Input for Automatic IOUTFS Calibration.
25
FSADJ1
External Full-Scale Current Output Adjust for DAC1 or Full-Scale Current Output Adjust Reference for
Automatic IOUTFS Calibration.
26
AGND
Analog Ground.
27
IOUTP1
DAC1 Current Output, Positive Side.
Rev. A | Page 11 of 48
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