datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

AD9102BCPZRL7 View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
AD9102BCPZRL7 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Data Sheet
AD9102
DIGITAL TIMING SPECIFICATIONS (1.8 V)
TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless
otherwise noted.
Table 4.
Parameter
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO
Setup Time CS to SCLK
Min
Typ
Max
Unit
180
MSPS
80
MHz
6.25
ns
6.25
ns
4.0
ns
5.0
ns
8.8
ns
4.0
ns
INPUT/OUTPUT SIGNAL SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments Min
Typ
Max
Unit
CMOS INPUT LOGIC LEVEL (SCLK, CS, SDIO,
SDO/SDI2/DOUT, RESET, TRIGGER)
Input VIN Logic High
DVDD = 1.8 V
1.53
V
DVDD = 3.3 V
2.475
V
Input VIN Logic Low
DVDD = 1.8 V
DVDD = 3.3 V
0.27
V
0.825
V
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO/SDI2/DOUT)
Output VOUT Logic High
Output VOUT Logic Low
DVDD = 1.8 V
1.79
DVDD = 3.3 V
3.28
DVDD = 1.8 V
DVDD = 3.3 V
V
V
0.25
V
0.625
V
DAC CLOCK INPUT (CLKP, CLKN)
Minimum Peak-to-Peak Differential Input Voltage,
VCLKP/VCLKN
Maximum Voltage at VCLKP or VCLKN
Minimum Voltage at VCLKP or VCLKN
Common-Mode Voltage
Generated on Chip
150
mV
VDVDD
V
VDGND
V
0.9
V
Rev. 0 | Page 5 of 36
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]