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AD9102-EBZ View Datasheet(PDF) - Analog Devices

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AD9102-EBZ Datasheet PDF : 36 Pages
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AD9102
Data Sheet
DC SPECIFICATIONS (1.8 V)
TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
RESOLUTION
ACCURACY @ 1.8 V
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
DAC OUTPUTS
Offset Error
Gain Error Internal Reference—No Automatic IOUTFS Calibration
Full-Scale Output Current
VCC = 1.8 V
Output Resistance
Output Compliance Voltage
DAC TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE OUTPUT
Internal Reference Voltage with AVDD = 1.8 V
Output Resistance
REFERENCE INPUT
Voltage Compliance
Input Resistance External Reference Mode
Min
Typ
Max
Unit
14
Bits
±1.5
LSB
±1.4
LSB
±0.00025
% of FSR
−1.0
+1.0
% of FSR
2
4
4
mA
200
MΩ
−0.5
+1.0
V
±228
±131
ppm/°C
ppm/°C
0.8
1.0
1.2
V
10
0.1
1
1.25
V
DIGITAL TIMING SPECIFICATIONS (3.3 V)
TMIN to TMAX; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2; IOUTFS = 8 mA; maximum sample rate,
unless otherwise noted.
Table 3.
Parameter
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO
Setup Time CS to SCLK
Min
Typ
Max
Unit
180
MSPS
80
MHz
6.25
ns
6.25
ns
4.0
ns
5.0
ns
6.2
ns
4.0
ns
Rev. 0 | Page 4 of 36
 

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