AD9058AKD View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
AD9058AKD Datasheet PDF : 11 Pages
| |||
AD9058
+5V
1
3
AD580
2
10k⍀
10k⍀
20k⍀
ANALOG
IN A
؎0.125V
0.1F
50⍀
1/2
AD708
400⍀
AD9618
ENCODE
+5V
150⍀
2N3904
10
ENCODE
A
10⍀
0.1F
3
+VREF A
43
+VREF B
5⍀
؎1V
6 AIN A
ANALOG
IN B
؎0.125V
1/2
AD708
50⍀
20k⍀
150⍀
400⍀
10k⍀
2N3906 0.1F
–5V
8
–VREF A
38
–VREF B
–1V
AD9618
5k⍀
0.1F
؎1V
40 AIN B
COMP
1
AD9058
(J-LEAD)
74ACT04
50k⍀
1k⍀
10pF
36
ENCODE
B
+VS
5, 9, 22,
24, 37, 41
0.1F
D0A(LSB)
18
17
16
15
14
13
12
D7A(MSB) 11
D0B(LSB)
D7B(MSB)
–VS
28
29
30
31
32
33
34
35
7, 20,
26, 39
0.1F
+5V
RZ1
8
CLOCK
RZ2
8
–5V
1N4001
CLOCK
(SEE TEXT)
4, 19, 21,
25, 27, 42
Figure 3. AD9058 Using External Voltage References
The on-board voltage reference, +VINT, is a band gap reference
that has sufficient drive capability for both reference ladders.
It provides a 2 V reference that can drive both ADCs in the
AD9058 for unipolar positive operation (0 V to 2 V).
USING THE AD9058
Refer to Figure 2. Using the internal voltage reference con-
nected to both ADCs as shown reduces the number of external
components required to create a complete data acquisition
system. The input ranges of the ADCs are positive unipolar
in this configuration, ranging from 0 V to 2 V. Bipolar input
signals are buffered, amplified, and offset into the proper input
range of the ADC using a good low distortion amplifier such
as the AD9617 or AD9618.
The AD9058 offers considerable flexibility in selecting the analog
input ranges of the ADCs; the two independent ADCs can even
have different input ranges if required. In Figure 3, the AD9058
is shown configured for ± 1 V operation.
The “Reference Ladder Offset” shown in the specifications table
refers to the error between the voltage applied to the +VREF (top)
or –VREF (bottom) of the reference ladder and the voltage required
at the analog input to achieve a 1111 1111 or 0000 0000 transi-
tion. This indicates the amount of adjustment range that must be
designed into the reference circuit for the AD9058.
The diode shown between ground and –VS is normally reverse-
biased and is used to prevent latch-up. Its use is recommended
for applications in which power supply sequencing might allow
+VS to be applied before –VS; or the +VS supply is not current
limited. If the negative supply is allowed to float (the +5 V supply
is powered up before the –5 V supply), substantial +5 V supply
current will attempt to flow through the substrate (VS supply con-
tact) to ground. If this current is not limited to <500 mA, the part
may be destroyed. The diode prevents this potentially destructive
condition from occurring.
Timing
Refer to the AD9058 Timing Diagram, Figure 4. The AD9058
provides latched data outputs with no pipeline delay. To conserve
power, the data outputs have relatively slow rise and fall times.
When designing system timing, it is important to observe (1) setup
and hold times; and (2) the intervals when data is changing.
Figure 3 shows 2 kΩ pull-down resistors on each of the D0–D7
output data bits. When operating at conversion rates higher than
40 MSPS, these resistors help equalize rise and fall times and
ease latching the output data into external latches. The 74ACT
logic family devices have short setup and hold times and are the
recommended choices for speeds of 40 MSPS or more.
Layout
To ensure optimum performance, a single low impedance ground
plane is recommended. Analog and digital grounds should be con-
nected together and to the ground plane at the AD9058 device.
Analog and digital power supplies should be bypassed to ground
through 0.1 μF ceramic capacitors as close to the unit as possible.
For prototyping or evaluation, surface-mount sockets are available
from Methode Electronics, Inc. (Part No. 213-0320602) for
evaluating AD9058 surface-mount packages. To evaluate the
REV. E
–7–
|
|
Share Link: 