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AD8188 View Datasheet(PDF) - Analog Devices

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AD8188 Datasheet PDF : 24 Pages
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AD8188/AD8189
These two techniques can also be combined. Typically, crosstalk
between the RGB signals from the same source is less objectionable
than crosstalk between two different sources. The former can
cause a color or luminance shift, but spatially, everything is
coherent. However, the crosstalk signals from two uncorrelated
sources can create ghost images that are far more objectionable.
A technique for minimizing crosstalk between two different
sources is to create two separate VMID circuits. Then, the inputs
from each source can be connected to their own VMID node,
minimizing crosstalk between sources.
AD8189
When using the gain-of-two AD8189 in a simple ac-coupled
application, there is a dynamic range limitation at the output
caused by its higher gain. At the output, the gain-of-two
produces a signal swing of 1.4 V, but the ac-coupling doubles
this required amount to 2.8 V. The AD8189 outputs can only
swing from 1.4 V to 3.6 V on a 5 V supply, so there are only
2.2 V of dynamic signal swing available at the output.
A standard means for reducing the dynamic range requirements
of an ac-coupled video signal is to use a dc restore. This circuit
works to limit the dynamic range requirements by clamping the
black level of the video signal to a fixed level at the input to the
amplifier. This prevents the video content of the signal from
varying the black level, as happens in a simple ac-coupled circuit.
DC RESTORE
After ac-coupling a video signal, it is necessary to use a dc
restore to establish where the black level is. Usually, this appears
at the end of a video signal chain. This dc restore circuit needs
to have the required accuracy for the system. It compensates for
all the offsets of the preceding stages. Therefore, if a dc restore
circuit is to be used only for dynamic range limiting, it does not
require great dc accuracy.
A dc restore circuit using the AD8189 is shown in Figure 56.
Two separate sources of RGB video are ac-coupled to the 0.1 μF
5V
input capacitors of the AD8189. The input points of the
AD8189 are switched to a 1.5 V reference by the ADG786,
which works in the following manner:
The SEL A/B signal selects the A or B input to the AD8189. It
also selects the switch positions in the ADG786 such that the
same selected inputs are connected to VREF when EN is low.
During the horizontal interval, all of the RGB input signals are
at a flat black level. A logic signal that is low during HSYNC is
applied to the EN of the ADG786. This closes the switches and
clamps the black level to 1.5 V. At all other times, the switches
are off and the node at the inputs to the AD8189 floats.
There are two considerations for sizing the input coupling
capacitors. One is the time constant during the H-pulse
clamping. The other is the droop associated with the capacitor
discharge due to the input bias current of the AD8189. For the
former, it is better to have a small capacitor, but for the latter, a
larger capacitor is better.
The on resistance of the ADG786 and the coupling capacitor
form the time constant of the input clamp. The ADG786 on
resistance is 5 Ω maximum. With a 0.1 μF capacitor, a time
constant of 0.5 μs is created. Thus, a sync pulse of greater than
2.5 μs causes less than 1% error. This is not critical because the
black level from successive lines is very close and the voltage
changes little from line to line.
A rough approximation of the horizontal line time for a graphics
system is 30 μs. This varies depending on the resolution and the
vertical rate. The coupling capacitor needs to hold the voltage
relatively constant during this time, while the input bias current
of the AD8189 discharges it.
The change in voltage is IB times the line time divided by the
capacitance. With an IB of 2.5 μA, a line time of 30 μs, and a
0.1 μF coupling capacitor, the amount of droop is 0.75 mV. This
is roughly 0.1% of the full video amplitude and is not observable
in the video display.
3V TO 5V 5V
5V
VREF
3.48k
1.5k
1.5V
+
10µF 0.1µF
VDD
ADG786
S1A
D1
S1B
S2A
D2
S2B
REDA
GRNA
BLUA
0.1µF
0.1µF
0.1µF
VREF
IN0A DVCC
IN1A
IN2A
VCC
AD8189
OUT0
×2
RED
VREF
×2
OUT1 GRN
2.4V MIN
HSYNC
S3A
D3
S3B
GND
VSS
LOGIC
EN A0 A1 A2
REDB
GRNB
BLUB
0.1µF
0.1µF
0.1µF
IN0B
IN1B
×2
OUT2 BLU
IN2B
DGND VEE SEL A/B OE
0.8V MIN
SEL A/B
Figure 56. AD8189 AC-Coupled with DC Restore
Rev. 0 | Page 19 of 24
 

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