AD8004AN_99 View Datasheet(PDF) - Analog Devices
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AD8004AN_99 Datasheet PDF : 16 Pages
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AD8004
DRIVING CAPACITIVE LOADS
The AD8004 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
settling response is obtained by the addition of a small series
resistance as shown in Figure 31. The accompanying graph
shows the optimum value for RSERIES vs. capacitive load. It is
worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of RSERIES and CL.
1k⍀
1k⍀
AD8004
RSERIES
RL
1k⍀
CL
Figure 31. Driving Capacitive Load
40
30
20
10
0
5
10
15
20
25
CL – pF
Figure 32. Recommended RSERIES vs. Capacitive Load for
≤ 30 ns Settling to 0.1%
OPTIMIZING FLATNESS
The fine scale gain flatness and –3 dB bandwidth is affected by
RFEEDBACK selection as is normal of current feedback amplifiers.
With exception of gain = +1, the AD8004 can be adjusted for
either maximal flatness with modest closed-loop bandwidth or
for mildly peaked-up frequency response with much more band-
width. Figure 33 shows the effect of three evenly spaced RF
changes upon gain = +1 and gain = +2. Table I shows the
recommended component values for achieving maximally flat
frequency response as well as a faster slightly peaked-up fre-
quency response.
Printed circuit board parasitics and device lead frame parasitics
also control fine scale gain flatness. The AD8004R package
because of its small lead frame offers superior parasitics relative
to the N package. In the printed circuit board environment,
parasitics such as extra capacitance caused by two parallel and
vertical flat conductors on opposite PC board sides in the
region of the summing junction will cause some bandwidth
extension and/or increased peaking. In noninverting gains, the
effect of extra capacitance on summing junctions is far more
pronounced than versus inverting gains. Figure 34 shows an
example of this. Note that only 1 pF of added junction capaci-
tance causes about a 70% bandwidth extension and additional
peaking on a gain = +2. For an inverting gain = –2, 5 pF of
additional summing junction capacitance caused a small 10%
bandwidth extension.
Extra output capacitive loading also causes bandwidth exten-
sions and peaking. The effect is more pronounced with less
resistive loading from the next stage. Figure 35 shows the effect
of direct output capacitive loads for gains of +2 and –2. For both
gains CLOAD was set to 10 pF or 0 pF (no extra capacitive loading).
For each of the four traces in Figure 35 the resistive loads were
100 Ω. Figure 36 also shows capacitive loading effects only
with a lighter output resistive load. Note that even though
bandwidth is extended 2×, the flatness dramatically suffers.
G = +1
RF = 1.1k⍀
RF = 909⍀
+2
RF = 698⍀
+1
0
–1
+1
G = +2
0
RF = 604⍀
–2
–3
–1
–4
VIN = 50mV rms
RF = 1.10k⍀
–2 VS = ؎5V
–5
RL = 100⍀
–3 R PACKAGE
–6
–4
RF = 845⍀
–7
–5
–8
1
10
40
100
500
FREQUENCY – MHz
Figure 33. RFEEDBACK vs. Frequency Response, G = +1/+2
G = +2
+2
G = –2
0
+2
CJ = 1pF
0
CJ = 0 –2
–4
–2
VIN = 50mV rms
–4 RL = 100⍀
؎5VS
–6
–6
–8
CJ = 5.1pF
–10
–8
–12
CJ = 0
–10
–14
–12
–14
1
10
40
100
500
FREQUENCY – MHz
Figure 34. Frequency Response vs. Added Summing
Junction Capacitance
–10–
REV. B
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