AD800 View Datasheet(PDF) - Analog Devices
Part Name
Description
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AD800 Datasheet PDF : 12 Pages
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AD800/AD802
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Input Voltage (Pin 16 or Pin 17 to VCC) . . . . VEE to +300 mV
Maximum Junction Temperature
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . +175°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C
ESD Rating
AD800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 V
AD802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to an absolute
maximum rating condition for an extended period may adversely affect device
reliability.
DATAOUT 50%
(PIN 2)
CLKOUT 50%
(PIN 5)
SETUP TIME
tSU
RECOVERED CLOCK
SKEW, tRCS
Figure 1. Recovered Clock Skew and Setup
(See Previous Page)
PIN DESCRIPTIONS
Number Mnemonic Description
1
DATAOUT Differential Retimed Data Output
2
DATAOUT Differential Retimed Data Output
3
VCC2
Digital Ground
4
CLKOUT Differential Recovered Clock Output
5
CLKOUT Differential Recovered Clock Output
6
VEE
Digital VEE
7
VEE
Digital VEE
8
VCC1
Digital Ground
9
AVEE
Analog VEE
10
ASUBST Analog Substrate
11
CF2
Loop Damping Capacitor Input
12
CF1
Loop Damping Capacitor Input
13
AVCC
Analog Ground
14
VCC1
Digital Ground
15
VEE
Digital VEE
16
DATAIN Differential Data Input
17
DATAIN Differential Data Input
18
SUBST
Digital Substrate
19
FRAC
Differential Frequency Acquisition
Indicator Output
20
FRAC
Differential Frequency Acquisition
Indicator Output
THERMAL CHARACTERISTICS
θJC
θJA
SOIC Package
Cerdip Package
22°C/W
25°C/W
75°C/W
90°C/W
Use of a heatsink may be required depending on operating
environment.
GLOSSARY
Maximum and Minimum Specifications
Maximum and minimum specifications result from statistical
analyses of measurements on multiple devices and multiple test
systems. Typical specifications indicate mean measurements.
Maximum and minimum specifications are calculated by adding
or subtracting an appropriate guardband from the typical
specification. Device-to-device performance variation and test
system-to-test system variation contribute to each guardband.
Nominal Center Frequency
This is the frequency that the VCO will operate at with no input
signal present and the loop damping capacitor, CD, shorted.
Tracking Range
This is the range of input data rates over which the PLL will
remain in lock.
Capture Range
This is the range of input data rates over which the PLL can
acquire lock.
Static Phase Error
This is the steady-state phase difference, in degrees, between the
recovered clock sampling edge and the optimum sampling
instant, which is assumed to be halfway between the rising and
falling edges of a data bit. Gate delays between the signals that
define static phase error, and IC input and output signals
prohibit direct measurement of static phase error.
Data Transition Density,
This is a measure of the number of data transitions, from “0” to
“1” and from “1” to “0,” over many clock periods. ρ is the ratio
(0 ≤ ρ ≤ 1) of data transitions to clock periods.
Jitter
This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms, or
Unit Intervals (UI). Jitter on the input data can cause dynamic
phase errors on the recovered clock sampling edge. Jitter on the
recovered clock causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a
specific pattern or some psuedo-random input data sequence
(PRN Sequence).
Jitter Tolerance
Jitter tolerance is a measure of the PLL’s ability to track a jittery
input data signal. Jitter on the input data is best thought of as
phase modulation, and is usually specified in unit intervals.
ORDERING GUIDE
Device
Fractional Loop
Center Frequency Bandwidth
Description
AD800-45BQ
AD800-52BR
AD802-155BR
AD802-155KR
44.736 MHz
51.84 MHz
155.52 MHz
155.52 MHz
0.1%
0.1%
0.08%
0.08%
20-Pin Cerdip
20-Pin Plastic SOIC
20-Pin Plastic SOIC
20-Pin Plastic SOIC
Operating Temperature
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
Package Option
Q-20
R-20
R-20
R-20
REV. B
–3–
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