AD7764 View Datasheet(PDF) - Analog Devices
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AD7764 Datasheet PDF : 32 Pages
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CLOCKING THE AD7764
The AD7764 requires an external low jitter clock source. This
signal is applied to the MCLK pin. An internal clock signal
(ICLK) is derived from the MCLK input signal. The ICLK
controls the internal operation of the AD7764. The maximum
ICLK frequency is 20 MHz. To generate the ICLK
ICLK = MCLK/2
For output data rates equal to those used in audio systems, a
12.288 MHz ICLK frequency can be used. As shown in Table 6,
output data rates of 96 kHz and 48 kHz are achievable with this
ICLK frequency.
MCLK JITTER REQUIREMENTS
The MCLK jitter requirements depend on a number of factors
and are given by
t j(rms)
=
2×π×
f IN
OSR
×10 SNR (dB)
20
where:
OSR = oversampling ratio = fICLK/ODR.
fIN = maximum input frequency.
SNR(dB) = target SNR.
Example 1
This example can be taken from Table 6, where:
ODR = 312.5 kHz.
fICLK = 20 MHz.
fIN (max) = 156.25 kHz.
SNR = 104 dB.
t
j(rms)
=
2×
64
π ×156.25 ×103
×105.2
= 51.41 ps
This is the maximum allowable clock jitter for a full-scale,
156.25 kHz input tone with the given ICLK and output
data rate.
Example 2
Take a second example from Table 6, where:
ODR = 48 kHz.
fICLK = 12.288 MHz.
fIN (max) = 19.2 kHz.
SNR = 109 dB.
AD7764
t j(rms)
=
256
2 × π ×19.2 ×103 ×105.45
= 470 ps
The input amplitude also has an effect on these jitter figures.
For example, if the input level is 3 dB below full-scale, the
allowable jitter is increased by a factor of √2, increasing the first
example to 57.75 ps rms. This happens when the maximum
slew rate is decreased by a reduction in amplitude.
Figure 44 and Figure 45 illustrate this point, showing the
maximum slew rate of a sine wave of the same frequency, but
with different amplitudes.
1.0
0.5
0
–0.5
–1.0
Figure 44. Maximum Slew Rate of Sine Wave
with Amplitude of 2 V p-p
1.0
0.5
0
–0.5
–1.0
Figure 45. Maximum Slew Rate of Same Frequency Sine Wave
with Amplitude of 1 V p-p
Rev. 0 | Page 25 of 32
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