AD7545AN View Datasheet(PDF) - Intersil
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AD7545AN Datasheet PDF : 7 Pages
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AD7545
bus systems, data on the data bus is not always valid for the
whole period during which WR is low and as a result invalid
data can briefly occur at the D/A converter inputs during a
write cycle. Such invalid data can cause unwanted glitches
at the output of the D/A converter. The solution to this prob-
lem, if it occurs, is to retime the write pulse (WR) so that it
only occurs when data is valid.
The choice of the operational amplifiers in Figure 4 and Figure
5 depends on the application and the trade off between
required precision and speed. Below is a list of operational
amplifiers which are good candidates for many applications.
The main selection criteria for these operational amplifiers is to
have low VOS, low VOS drift, low bias current and low settling
time.
Another cause of digital glitches is capacitive coupling from
the digital lines to the OUT1 and AGND terminals. This
should be minimized by isolating the analog pins of the
AD7545 (pins 1, 2, 19, 20) from the digital pins by a ground
track run between pins 2 and 3 and between pins 18 and 19
of the AD7545. Note how the analog pins are at one end of
the package and separated from the digital pins by VDD and
DGND to aid isolation at the board level. On-chip capacitive
coupling can also give rise to crosstalk from the digital to
analog sections of the AD7545, particularly in circuits with
high currents and fast rise and fall times. This type of
crosstalk is minimized by using VDD = +5V. However, great
care should be taken to ensure that the +5V used to power
the AD7545 is free from digitally induces noise.
These amplifiers need to maintain the low nonlinearity and
monotonic operation of the D/A while providing enough
speed for maximum converter performance.
Operational Amplifiers
HA5127
HA5137
HA5147
HA5170
Ultra Low Noise, Precision
Ultra Low Noise, Precision, Wide Band
Ultra Low Noise, Precision, High Slew Rate
Precision, JFET Input
TABLE 1. RECOMMENDED TRIM RESISTOR VALUES vs
GRADES FOR VDD = +5V
TRIM RESISTOR
J, A, S
K, B
Temperature Coefficients
R1
500Ω
200Ω
The gain temperature coefficient of the AD7545 has a maxi-
mum value of 5ppm/oC and a typical value of 2ppm/oC. This
corresponds to worst case gain shifts of 2 LSBs and
0.8 LSBs respectively over a 100oC temperature range.
When trim resistors R1 and R2 are used to adjust full scale
range, the temperature coefficient of R1 and R2 should also
be taken into account.
Basic Applications
Figures 5 and 6 show simple unipolar and bipolar circuits
using the AD7545. Resistor R1 is used to trim for full scale.
Capacitor C1 provides phase compensation and helps pre-
vent overshoot and ringing when using high speed op amps.
Note that the circuits of Figures 5 and 6 have constant input
impedance at the VREF terminal.
The circuit of Figure 4 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in
the range 0V to -VIN (note the inversion introduced by the op
amp) or VIN can be an AC signal in which case the circuit
behaves as an attenuator (2-Quadrant Multiplier). VIN can be
any voltage in the range -20V ≤ VIN ≤ +20V (provided the op
amp can handle such voltages) since VREF is permitted to
exceed VDD. Table 2 shows the code relationship for the
circuit of Figure 4.
Figure 5 and Table 3 illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code and inverter U1 on the MSB line con-
verts 2’s complement input code to offset binary code. If appro-
priate, inversion of the MSB may be done in software using an
exclusive -OR instruction and the inverter omitted. R3, R4 and
R5 must be selected to match within 0.01% and they should be
the same type of resistor (preferably wire-wound or metal foil),
so that their temperature coefficients match. Mismatch of R3
value to R4 causes both offset and full scale error. Mismatch of
R5 to R4 and R3 causes full scale error.
R2
150Ω
68Ω
TABLE 2. UNIPOLAR BINARY CODE TABLE FOR CIRCUIT OF
FIGURE 4
BINARY NUMBER IN DAC
REGISTER
1111
1111
1111
1000
0000
0000
0000
0000
0001
0000
0000
0000
ANALOG OUTPUT
–VI
N
44----00---99----56-
–VIN
24----00---49----86-
=
–12-- VIN
–VI N
4----0--1-9----6-
0V
TABLE 3. 2’S COMPLEMENT CODE TABLE FOR CIRCUIT OF
FIGURE 5
DATA INPUT
0111
1111
1111
0000
0000
0001
0000
0000
0000
1111
1111
1111
1000
0000
0000
ANALOG OUTPUT
+
VIN
•
22----00---44----78-
+
VIN
•
2----0--1-4----8-
0V
–VI
N
•
2----0--1-4----8-
–VI
N
•
22----00---44----88-
10-14
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