AD73322L View Datasheet(PDF) - Analog Devices

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Description

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AD73322L

Low Cost, Low Power CMOS General-Purpose Dual Analog Front End

Analog Devices 

AD73322L

t1

t2

t3

Figure 1. MCLK Timing

100␮A IOL

TO OUTPUT

PIN

CL

15pF

100␮A IOH

2.1V

Figure 2. Load Circuit for Timing Specifications

SE (I)

THREE-

SCLK (O) STATE

SDIFS (I)

SDI (I)

THREE-

SDOFS (O) STATE

THREE-

STATE

SDO (O)

t1

t2

t3

MCLK

SCLK*

t 13

t5

t6

t4

* SCLK IS INDIVIDUALLY PROGRAMMABLE

IN FREQUENCY (MCLK/4 SHOWN HERE).

Figure 3. SCLK Timing

t7

t8

D15

D14

t8

t7

D1

D0

t9

t 10

t 12

t 11

D15

D2

D1

D0

Figure 4. Serial Port (SPORT)

D15

D15

D14

–6–

REV. 0

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