AD73322L View Datasheet(PDF) - Analog Devices

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AD73322L

Low Cost, Low Power CMOS General-Purpose Dual Analog Front End

Analog Devices 

AD73322L

APPENDIX A

DAC Timing Control Example

The AD73322L’s DAC is loaded from the DAC register con-

tents just before the ADC register contents are loaded to the

serial register (SDOFS going high). This default DAC load

position can be advanced in time to occur earlier with respect to

the SDOFS going high. Figure 45 shows an example of the

ADC unload and DAC load sequence. At time t1 the SDOFS is

raised to indicate that a new ADC word is ready. Following the

SDOFS pulse, 16 bits of ADC data are clocked out on SDO in

the subsequent 16 SCLK cycles finishing at time t2 where the

DSP’s SPORT will have received the 16-bit word. The DSP

may process this information and generate a DAC word to be

sent to the AD73322L. Time t3 marks the beginning of the

sequence of sending the DAC word to the AD73322L. This

sequence ends at time t4 where the DAC register will be updated

from the 16 bits in the AD73322L’s serial register. However,

the DAC will not be updated from the DAC register until time

t5, which may not be acceptable in certain applications. In order

to reduce this delay and load the DAC at time t6, the DAC

advance register can be programmed with a suitable setting

corresponding to the required time advance (refer to Table X

for details of DAC Timing Control settings).

SE

SCLK

SDOFS

SDO

SDIFS

SDI

ADC WORD

DAC WORD

DATA REGISTER

UPDATE

DAC LOAD

FROM DAC REGISTER

t1

t2

t3

t4 t6

t5

Figure 39. DAC Timing Control

–34–

REV. 0

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