AD73322L
CONTROL REGISTER A
CONTROL REGISTER B
Table XIII. Control Register A Description
7
6
5
4
3
2
1
RESET DC2
DC1
DC0
SLB
DLB
MM
Bit Name
Description
0 DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)
1 MM
Mixed Mode (0 = Off; 1 = Enabled)
2 DLB
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
3 SLB
SPORT Loop-Back Mode (0 = Off; 1 = Enabled)
4 DC0
Device Count (Bit 0)
5 DC1
Device Count (Bit 1)
6 DC2
Device Count (Bit 2)
7 RESET
Software Reset (0 = Off; 1 = Initiates Reset)
0
DATA/
PGM
Table XIV. Control Register B Description
7
6
5
4
3
2
1
0
—
RU PUREF PUDAC PUADC PUIA PUAGT PU
Bit Name
0 DIR0
1 DIR1
2 SCD0
3 SCD1
4 MCD0
5 MCD1
6 MCD2
7 CEE
Description
Decimation/Interpolation Rate (Bit 0)
Decimation/Interpolation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = Off; 1 = Enabled)
CONTROL REGISTER C
Table XV. Control Register C Description
7
MUTE
6
OGS2
5
OGS1
4
3
OGS0 RMOD
2
IGS2
1
IGS1
0
IGS0
Bit Name
0 PU
1 PUAGT
2 PUIA
3 PUADC
4 PUDAC
5 PUREF
6 RU
7—
Description
Power-Up Device (0 = Power-Down; 1 = Power On)
Analog Gain Tap Power (0 = Power-Down; 1 = Power On)
Input Amplifier Power (0 = Power-Down; 1 = Power On)
ADC Power (0 = Power-Down; 1 = Power On)
DAC Power (0 = Power-Down; 1 = Power On)
REF Power (0 = Power-Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Reserved, must be programmed to 0.
–18–
REV. 0