|AD7813YNZ||2.7 V to 5.5 V, 400 kSPS 8-/10-Bit Sampling ADC|
|AD7813YNZ Datasheet PDF : 12 Pages |
During the acquisition phase the sampling capacitor must be
charged to within a 1/2 LSB of its final value. The time it takes
to charge the sampling capacitor (TCHARGE) is given by the
TCHARGE = 7.6 × (R2 + 125 Ω) × 3.5 pF
For small values of source impedance, the settling time associ-
ated with the sampling circuit (100 ns) is, in effect, the acquisi-
tion time of the ADC. For example, with a source impedance
(R2) of 10 Ω the charge time for the sampling capacitor is
approximately 4 ns. The charge time becomes significant for
source impedances of 2 kΩ and greater.
AC Acquisition Time
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of source impedance will cause the
THD to degrade at high throughput rates.
ADC TRANSFER FUNCTION
The output coding of the AD7813 is straight binary. The
designed code transitions occur at successive integer LSB values
(i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/1024. The
ideal transfer characteristic for the AD7813 is shown in Figure 7.
1LSB = VREF/1024
Figure 7. Transfer Characteristic
The AD7813 has a 1.5 µs power-up time. When VDD is first
connected, the AD7813 is in a low current mode of operation.
In order to carry out a conversion the AD7813 must first be
powered up. The ADC is powered up by a rising edge on an
internally generated CONVST signal, which occurs as a result
of a rising edge on the external CONVST pin. The rising edge
of the external CONVST signal initiates a 1.5 µs pulse on the
internal CONVST signal. This pulse is present to ensure the
part has enough time to power up before a conversion is initi-
ated, as a conversion is initiated on the falling edge of gated
CONVST. See Timing and Control section. Care must be taken
to ensure that the CONVST pin of the AD7813 is logic low
when VDD is first applied.
When operating in Mode 2, the ADC is powered down at the
end of each conversion and powered up again before the next
conversion is initiated. (See Figure 8.)
Figure 8. Power-Up Times
POWER VS. THROUGHPUT RATE
By operating the AD7813 in Mode 2, the average power con-
sumption of the AD7813 decreases at lower throughput rates.
Figure 9 shows how the Automatic Power-Down is implemented
using the external CONVST signal to achieve the optimum
power performance for the AD7813. The AD7813 is operated
in Mode 2, and the duration of the external CONVST pulse is
set to be equal to or less than the power-up time of the device.
As the throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
1.5s t CONVERT
100s @ 10kSPS
Figure 9. Automatic Power-Down
For example, if the AD7813 is operated in a continuous sam-
pling mode, with a throughput rate of 10 kSPS, the power con-
sumption is calculated as follows. The power dissipation during
normal operation is 10.5 mW, VDD = 3 V. If the power-up time
is 1.5 µs and the conversion time is 2.3 µs, the AD7813 can then
be said to dissipate 10.5 mW for 3.8 µs (worst-case) during each
conversion cycle. If the throughput rate is 10 kSPS, the cycle
time is 100 µs and the average power dissipated during each
cycle is (3.8/100) × (10.5 mW) = 400 µW.
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