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AD7813YNZ View Datasheet(PDF) - Analog Devices

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AD7813YNZ Datasheet PDF : 12 Pages
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AD7813
TIMING CHARACTERISTICS1, 2 (–40؇C to +105؇C, unless otherwise noted)
Parameter
tPOWER-UP
t1
t2
t3
t4
t5
t63
t73, 4
t8
t93
VDD = 3 V ؎ 10%
1.5
2.3
20
30
0
0
10
10
5
10
50
VDD = 5 V ؎ 10%
1.5
2.3
20
30
0
0
10
10
5
10
50
Unit
µs (max)
µs (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
Conditions/Comments
Power-Up Time of AD7813 after Rising Edge of CONVST.
Conversion Time.
CONVST Pulsewidth.
CONVST Falling Edge to BUSY Rising Edge Delay.
CS to RD Setup Time.
CS Hold Time after RD High.
Data Access Time after RD Low.
Bus Relinquish Time after RD High.
Minimum Time Between MSB and LSB Reads.
Rising Edge of CS or RD to Falling Edge of CONVST Delay.
NOTES
1Sample tested to ensure compliance.
2See Figures 12, 13 and 14.
3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and
0.4 V or 2 V for VDD = 3 V ± 10%.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the Timing Characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
ABSOLUTE MAXIMUM RATINGS*
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND
(CONVST, RD, CS) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Digital Output Voltage to DGND
(BUSY, DB0–DB7) . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
REFIN to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Analog Input . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
200A
IOL
TO
OUTPUT
PIN
CL
50pF
200A
IOH
1.6V
Figure 1. Load Circuit for Digital Output Timing
Specifications
ORDERING GUIDE
Model
Linearity Package
Error Description
Package
Option
AD7813YN ± 1 LSB
AD7813YR ± 1 LSB
AD7813YRU ± 1 LSB
Plastic DIP
N-16
Small Outline IC
R-16A
Thin Shrink Small Outline RU-16
(TSSOP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7813 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–3–
 

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