AD362SD View Datasheet(PDF) - Analog Devices

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AD362SD

Precision Sample-and-Hold with 16-Channel Multiplexer

Analog Devices 

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\.0362 DESIGN

rhe AD362 consists of two 8-channel multiplexers, a differen-

:ial amplifier, a sample-and-hold with high-speed output buf-

:er, channel address latches and control logic as shown in

~igure 1. The multiplexers can be connected to the differential

lmplifier in either an 8-channel differential or 16-channel

;ingle-ended configuration. A unique fearure of the AD362 is

In internal analog switch controlled by a digital input that

Jerforms switching between single-ended and differential

nodes. This fearure allows a single AD362 to perform in

~ither mode without external hard-wire interconnections.

Of more significance is the ability to serve a mixtUre of both

;ingle-ended and differential sources with a single AD362 by

:Iynamically switching the input mode control.

'"'GW' A.ACOG '.PUTS

smaller capacitor will allow faster sample-and-hold response

but will decrease accuracy while a larger capacitor will in-

crease accuracy at slower conversion rates.

The output buffer is a high speed amplifier whose output

impedance remains low and constant at high frequencies.

Therefore, the AD362 may drive a fast, unbuffered, precision

ADC without loss of accuracy.

The AD362 is constructed on a substrate that includes thick-

film resistors for non-critical applications such as input pro-

tection and biasing. A separately-mounted laser-trimmed thin-

film resistor network is used to establish accurate gain and

high common-mode rejection. The metal package affords

electromagnetic and electrostatic shielding and is hermetically

welded at low temperatures. Welding eliminates the possibility

of contamination from solder particles or flux while low tem-

peratUre sealing maintains the accuracy of the laser-trimmed

thin-film resistors.

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:{ L Figure 1. A0362 Analog Input Section Functional Block

E Diagram and Pinout

TE88 Multiplexer channel address inputs are interfaced through a

THEORY OF OPERATION

Concept

The AD362 is intended to be used in conjunction with a high-

speed precision analog-to-digital converter to form a complete

data acquisition system (DAS) in microcircuit form. Figure 2

shows a general AD362-with-ADC DAS application.

AO362

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level-triggered ("transparent") input register. With a Logic "1"

at the Channel Select Latch input, the address signals feed

through the register to directly select the appropriate input

channel. This address information can be held in the register

by placing a Logic "0" on the Channel Select Latch input. In-

rernallogic monitors the status of the Single-Ended/Differential

Figure 2. AD362 with ADC as a Complete Data Acquisition

System

By dividing the data acquisition task into two sections, several

lode inp<lt and addresses the multiplexers accordingly.

. differential amplifier buffers the multiplexer outputs while

roviding high input impedance in b0th differential and. single-

i1ded modes. Amplifier gain and common mode rejection are

ctively laser-trimmed.

important advantages are realized. Performance of each design

is optimized for its specific function. Production yields are

increased thus decreasing costs. Furthermore, the standard

configuration packages plug into standard sockets and are

easier to handle than larger packages with higher pin counts.

lhe sample-and-hold is a high speed monolithic device that can

also function as a gated operational amplifier. Its uncommitted

differential inputs allow it to serve a second role as the output

subtractor in the differential amplifier. This eliminates one

amplifier and decreases drift, settling time and power consump-

Svstem Timine:

Figure 3 is a timing diagram for the AD362 connected as

shown in Figure 2 and operating at maximum conversion rate.

The ADC is assumed to be a conventional 12 bit type such as

the AD572 or AD ADC80.

tion. A Logic "1" on the Sample-and-Hold Command input

will cause the sample-and-hold to "freeze" the analog signal

while the ADC performs the conversion. Normally the Sample-

ADDRESS

and-Hold Command is connected to th~ ADC Status output

which is at Logic" 1" during conversion and Logic "0" be-

ADDRESS lATCH

~

tween conversions. For slowly-changing inputs, throughput

speed may be increased by grounding the Sample-and-Hold

CONVERT COMMAND

Command input instead of connecting it to the ADC status.

A Polystyrene hold capacitor is provided with each commer-

STATUS {SAMPlE.HOlD)

,.

cial temperatUre range device (AD362KD) while a Teflon ca-

pacitor is provided with units intended for operation at tempera-

tures up to 125°C (AD362SD). Use of an external capacitor

allows the user to make his own speed/accuracy tradeoff; a

GATED CLOCK

Figure 3. DAS Timing Diagram

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