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AD2S93BP View Datasheet(PDF) - Analog Devices

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Description
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AD2S93BP
ADI
Analog Devices ADI
AD2S93BP Datasheet PDF : 12 Pages
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AD2S93
Two-Wire LVDT Connection
This method should be used in cases where the sum of the
LVDT secondary output voltages (A + B) is not constant with
LVDT displacement over the desired stroke length. This method
of connection, shown in Figure 7, still maintains the ratiometric
operation and the insensitivity to variations in reference ampli-
tude and frequency. However, the phase shift between VREF
and V1 should be minimized to maintain accuracy (see Section
“PHASE SHIFT AND QUADRATURE EFFECTS”). Sug-
gested phase compensation circuits are shown in Figure 7.
PHASE SHIFT AND QUADRATURE EFFECTS
Reference to signal phase shift can be high in LVDTs, some-
times in the order of 70 degrees. If the converter is connected
as in Figures 5 and 6, any effects due to this phase shift are
minimized. This connection method, therefore, provides out-
standing benefits.
The additional gain error caused by reference to signal phase
shifts is given by:
(1 – cos θ) × 100% of FSR
where
θ = phase shift between VREF and DIFF.
When the phase shift between VREF and V1 is zero, additional
quadrature on the signal will have no effect on the converter.
This is another benefit of the conversion method. For example,
when a REF lags (A–B) by approximately 10°, the gain error is
approximately 1%. When (A–B) lags REF by approximately
10°, the gain error is approximately 2%.
REMOTE MULTIPLE SENSOR INTERFACING
The DATA output of the AD2S93 is held in a high impedance
state until CS is taken LO. This allows a user to operate the
AD2S93 in an application with more than one converter con-
nected on the same line. Figure 8 shows four LVDTs interfaced
to four AD2S93s. Excitation for the LVDT is provided locally
by an oscillator.
SCLK, DATA and two address lines are fed down low loss
cables suitable for communication links. The two address lines
are decoded locally into CS for the individual converters. Data
is received and transmitted using transmitters and receivers.
2-4 DECODING
A0
(74HC139)
4
CS1CS2 CS3 CS4
A1
LVDT
AD2S93
1
LVDT
4
AD2S93
2
SCLK
LVDT 4 AD2S93
3
DATA
LVDT 4 AD2S93
4
2
2
BUFFER
OSC
VDD
VSS
0V
Figure 8. Remote Sensor Interface
PHASE
SHIFT
CCT
OSC
PISTON
1
PHASE LEAD = ARCTAN 2π fRC
C
R
C1
C2
C3
R2
R6
REF
25 24 23 22 21 20 19
C4
R5
R7
NC 26
B 27
A 28
AGND 1
DIFF 2
R4 R3
GAIN 3
12k
LOS
4
VDD
PHASE LAG = ARCTAN 2 π fRC
R
C
AADD22SS9933
TOP VIEW
(Not to Scale)
18
DEMODOUT
17 VDD
+5V
0V
16 VSS
–5V
15 DGND
14 DIR
13 NULL
12 OVR
5 6 7 8 9 10 11
NC = NO CONNECT
Figure 7. Two-Wire LVDT Connection
REV. A
–9–
 

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