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AD2S93 View Datasheet(PDF) - Analog Devices

Part Name
Description
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AD2S93 Datasheet PDF : 12 Pages
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AD2S93
Parameter
Test Conditions
SERIAL CLOCK (SCLK)
SCK Input Rate
Maximum Read Rate (16 Bits)
Continuous
POWER SUPPLY
IDD
ISS
NOTES
1The signal input voltage maximum should always be set at 10% less than the reference input.
2Nominal + FS = VA–B = VREF/2, FS = –VA–B = VREF/2
3With G = 10; Sensitivity 34.2 µV pk/LSB
4Phase shift cause gain errors. “See Phase Shift and Quadrative Effects.”
Specifications subject to change without notice.
Min Typ Max
2
9.2
5
7
10
5
7
10
Units
MHz
µs
mA
mA
TIMING CHARACTERISTICS (VDD = +5 V ± 5%, AGND = DGND = 0 V, TA = –40°C to +85°C unless otherwise noted)
Parameter
AD2S93
t11
150
t2
600
t3
250
t4
250
t5
100
t6
600
t7
150
NOTE
1SCLK can only be applied after t2 has elapsed.
Units
ns max
ns min
ns min
ns min
ns max
ns min
ns max
Test Conditions
CS to DATA Enable
CS to 1st SCLK Positive Edge
SCLK High Pulse
SCLK Low Pulse
SCLK Positive Edge to DATA Valid
CS High Pulse Width
CS High to DATA High Z (Bus Relinquish)
CS
SCLK
DATA
t1
t2
t3
t4
MSB
t5
t6
t*
LSB
t7
t * = THE MINIMUM ACCESS TIME: USER DEPENDENT
TOTAL MAX READ TIME = t2 + 16. (t3 + t4 ) + t7
TOTAL MAX READ TIME = 600 +16 (250 + 250) + 150 ns
TOTAL MAX READ TIME = 600 + 8000 + 150 ns
TOTAL MAX READ TIME = 8.750 µs (SINGLE READ ONLY)
Timing Diagram
REV. A
–3–
 

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