|AD2S82ALP||Variable Resolution, Monolithic Resolver-to-Digital Converters|
|AD2S82ALP Datasheet PDF : 16 Pages |
To transfer data the INHIBIT input should be used. The data
will be valid 600 ns after the application of a logic “LO” to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic “HI”
state to enable the output latches to be updated.
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
The ENABLE input determines the state of the output data. A
logic “HI” maintains the output data pins in the high impedance
condition, and the application of a logic “LO” presents the data
in the latches to the output pins. The operation of the ENABLE
has no effect on the conversion process.
BYTE SELECT Input
The BYTE SELECT input on the AD2S82A selects the byte of
the position data to be presented at the data output DB1 to
DB8. The least significant byte will be presented on data output
DB9 to DB16 (with the ENABLE input taken to a logic “LO”)
regardless of the state of the BYTE SELECT pin. Note that
when the AD2S82A is used with a resolution less than 16 bits,
the unused data lines are pulled to a logic “LO.” A logic “HI”
on the BYTE SELECT input will present the eight most signifi-
cant data bits on data output DB1 and DB8. A logic “LO” will
present the least significant byte on data outputs 1 to 8, i.e.,
data outputs 1 to 8 will duplicate data outputs 9 to 16.
When the BYTE select pin is a logic “HI” on the AD2S81A, the
most significant byte is presented on Pins 8 to 15 (with the
ENABLE input taken to a logic “LO”). A logic “HI” presents
the 4 least significant bits on Pins 8 to 11 and places a logic
“LO” on Pins 12 to 15 (with the ENABLE input taken to a
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
As the output of the converter passes through the major carry,
i.e., all “1s” to all “0s” or the converse, a positive going edge on
the RIPPLE CLK output is initiated indicating that a revolu-
tion, or a pitch, of the input has been completed.
The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE
CLK is normally set high before a BUSY pulse and resets before
the next positive going edge of the next consecutive pulse.
If the AD2S81A/AD2S82A is being used in a pitch and revolu-
tion counting application, the ripple and busy will need to be
gated to prevent false decrement or increment (see Figure 2).
RIPPLE CLK is unaffected by INHIBIT.
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS “LO.”
Figure 2. Diode Transistor Logic Nand Gate
The DIRECTION (DIR) logic output indicates the direction of
the input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA, and RIPPLE CLK updates. DIR
can be considered as an asynchronous output and can make
multiple changes in state between two consecutive LSB update
cycles. This corresponds to a change in input rotation direction
but less than 1 LSB.
COMPLEMENT (AD2S82A Only)
The COMPLEMENT input is internally pulled to +12 V in the
INACTIVE STATE. It is pulled down to DIGITAL GROUND
(100 µA) to ACTIVATE.
When used in conjunction with DATA LOAD, strobing DATA
LOAD and COMPLEMENT pins to logic LO, will set the logic
HIGH bits of the AD2S82A counter to a LO state. Those bits of
the applied data which are logic LO will not change the corre-
sponding bits in the AD2S82A counter:
Initial Counter State
Applied Data Word
Counter State after Data Load
Initial Counter State
Applied Data Word
Counter State after Data Load and Complement
In order to read the output the following procedures should be
1. Place Outputs in high impedance (ENABLE = HI).
2. Present data to pins.
3. Pull DATA LOAD and COMPLEMENT pins to ground.
4. Wait 100 ns.
5. Remove data from pins.
6. Remove outputs from high impedance state (ENABLE =
7. Read outputs.
The only exception to this is when DIR changes while the
RIPPLE CLK is high. Resetting of the RIPPLE CLK will only
occur if the DIR remains stable for two consecutive positive
BUSY pulse edges.
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