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AD2S82A View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD2S82A Variable Resolution, Monolithic Resolver-to-Digital Converters ADI
Analog Devices ADI
AD2S82A Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
The following instructions describe how to select the external
components for the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest “preferred
value’’ component should be used and a 5% tolerance will not
degrade the overall performance of the converter. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. The components should
be connected as shown in Figure 1.
PC compatible software is available to help users select the optimum
component values for the AD2S81A and AD2S82A, and display the
transfer gain, phase and small step response.
For more detailed information and explanation, see the Circuit
Functions and Dynamic Performance section.
1. HF Filter (R1, R2, C1, C2)
The function of the HF filter is to remove any dc offset and
to reduce the amount of noise present on the signal inputs
to the AD2S81A/AD2S82A, reaching the Phase Sensitive
Detector and affecting the outputs. R1 and C2 may be omit-
ted—in which case R2 = R3 and C1 = C3, calculated below—
but their use is particularly recommended if noise from
switch mode power supplies and brushless motor drive is
Values should be chosen so that
15 kΩ ≤ R1 = R2 56 k
C1 = C2
2 π R1 fREF
and fREF = Reference Frequency
This filter gives an attenuation of three times at the input to
the phase sensitive detector.
2. Gain Scaling Resistor (R4)
If R1, C2 are fitted, then:
R4 =
100 × 109
where 100 × 10–9 = current/LSB
If R1, C2 are not fitted, then:
R4 = EDC
100 × 10–9
where EDC = 160 × 10–3 for 10 bits resolution
= 40 × 10–3 for 12 bits
= 10 × 10–3 for 14 bits
= 2.5 × 10–3 for 16 bits
= Scaling of the DC ERROR in volts
3. AC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,
with R3 in .
R3 = 100 k
C3 >
R 3 × fREF
4. Maximum Tracking Rate (R6)
The VCO input resistor R6 sets the maximum tracking rate
of the converter, and hence the velocity scaling as at the max
tracking rate, the velocity output will be 8 V.
Decide on your maximum tracking rate, “T,” in revolutions
per second. Note that “T” must not exceed the maximum
tracking rate or 1/16 of the reference frequency.
R6 = 6. 32 × 1010
T ×n
where n = bits per revolution
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
5. Closed-Loop Bandwidth Selection (C4, C5, R5)
a. Choose the closed-loop bandwidth (fBW) required
ensuring that the ratio of reference frequency to band-
width does exceed the following guidelines:
Ratio of Reference Frequency/Bandwidth
2.5 : 1
4 :1
6 :1
7.5 : 1
Typical values may be 100 Hz for a 400 Hz reference fre-
quency and 500 Hz to 1000 Hz for a 5 kHz reference
b. Select C4 so that
C4 =
R6 ×
with R6 in and fBW, in Hz selected above.
c. C5 is given by
C5 = 5 × C4 F
d. R5 is given by
R5 =
2 × π × f BW × C5
6. VCO Phase Compensation
The following values of C6 and R7 should be fitted.
C6 = 470 pF, R7 = 68
7. Offset Adjust
Offsets and bias currents at the integrator input can cause an
additional positional offset at the output of the converter of
1 arc minute typical, 5.3 arc minutes maximum. If this can be
tolerated, then R8 and R9 can be omitted from the circuit.
If fitted, the following values of R8 and R9 should be used:
R8 = 4.7 M, R9 = 1 Mpotentiometer
To adjust the zero offset, ensure the resolver is disconnected
and all the external components are fitted. Connect the COS
pin to the REFERENCE I/P and the SIN pin to the SIGNAL
GND and with the power and reference applied, adjust the
potentiometer to give all “0s” on the digital output bits.
The potentiometer may be replaced with select on test resistors
if preferred.
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