AD2S82A View Datasheet(PDF) - Analog Devices
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AD2S82A Datasheet PDF : 16 Pages
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AD2S81A/AD2S82A
CONNECTING THE CONVERTER
The power supply voltages connected to +VS and –VS pins
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to VL can be +5 V dc to +VS.
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +VS, –VS and ANALOG GND
adjacent to the converter. Recommended values are 100 nF
(ceramic) and 10 µF (tantalum). Also capacitors of 100 nF and
10 µF should be connected between +VL and DIGITAL GND
adjacent to the converter.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and
COS inputs, REFERENCE I/P and SIGNAL GND as shown
in Figure 7 and described in the Connecting the Resolver
section.
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the resolver to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GND and ANALOG GND are connected internally.
ANALOG GND and DIGITAL GND must be connected
externally.
The external components required should be connected as
shown in Figures 1a and 1b.
REFERENCE I/P
HP FILTER
C1
R2
C2
R1
C3
R3
OFFSET ADJUST
R9
+12V
–12V
R8
R4
AC ERROR
O/P
DEMOD
I/P
DEMOD
O/P
INTEGRATOR
I/P
BANDWIDTH
SELECTION
C5
C4
R5
SIN I/P
SIGNAL GND
COS I/P
ANALOG GND
RIPPLE CLK
+12V
–12V
COMP
A1
SEGMENT
SWITCHING
R-2R DAC
A3
A2
16-BIT UP/DOWN COUNTER
OUTPUT DATA LATCH
DATA SC1 SC2
LOAD
ENABLE
16 DATA BITS
PHASE-SENSITIVE
DETECTOR
AD2S82A
INTEGRATOR
O/P
R6
VELOCITY
SIGNAL
VCO
DATA TRANSFER
LOGIC
+5V DIGITAL BUSY VCO DIR INHIBIT
BYTE
GND
O/P
SELECT
VCO I/P
R7
C6
TRACKING
RATE
SELECTION
Figure 1a. AD2S82A Connection Diagram
SIN I/P
SIGNAL GND
COS I/P
RIPPLE CLK
+12V
–12V
REFERENCE I/P
HP FILTER
C1
R2
C2
R1
C3
R3
OFFSET ADJUST
R9
+12V
–12V
R8
R4
AC ERROR
O/P
DEMOD
I/P
DEMOD
O/P
INTEGRATOR
I/P
BANDWIDTH
SELECTION
C5
C4
R5
A1
SEGMENT
SWITCHING
R-2R DAC
A3
A2
PHASE-SENSITIVE
DETECTOR
AD2S81A
16-BIT UP/DOWN COUNTER
OUTPUT DATA LATCH
VCO
DATA TRANSFER
LOGIC
ENABLE
8 DATA BITS
BYTE +5V DIGITAL BUSY DIR INHIBIT
SELECT
GND
Figure 1b. AD2S81A Connection Diagram
INTEGRATOR
O/P
R6
VELOCITY
SIGNAL
VCO I/P
R7
C6
TRACKING
RATE
SELECTION
–6–
REV. B
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