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AD2S82ALP View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD2S82ALP Variable Resolution, Monolithic Resolver-to-Digital Converters ADI
Analog Devices ADI
AD2S82ALP Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
Ratio Multiplier
The ratio multiplier is the input section of the AD2S81A/
AD2S82A and compares the signal from the resolver input
angle, θ, to the digital angle, φ, held in the counter. Any differ-
ence between these two angles results in an analog voltage at
the AC ERROR OUTPUT. This circuit function has histori-
cally been called a “Control Transformer” as it was originally
performed by an electromechanical device known by that name.
The AC ERROR signal is given by
A1 sin (θ φ) sin ωt
where ω = 2 π fREF
fREF = reference frequency
A1, the gain of the ratio multiplier stage is 14.5.
So for 2 V rms inputs signals
AC ERROR output in volts/(bit of error)
n 
Where n = bits per rev
= 1,024 for 10-bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
Giving an AC ERROR O/P
= 178 mV/bit @ 10-bits resolution
= 44.5 mV/bit @ 12 bits
= 11.125 mV/bit @ 14 bits
= 2.78 mV/bit @ 16 bits
The ratio multiplier will work in exactly the same way whether
the AD2S81A/AD2S82A is connected as a tracking converter or
as a control transformer, where data is preset into the counters
using the DATA LOAD pin.
HF Filter
The AC ERROR OUTPUT may be fed to the PSD via a simple
ac coupling network (R2, C1) to remove any dc offset at this
point. Note, however, that the PSD of the AD2S81A/AD2S82A
is a wideband demodulator and is capable of aliasing HF noise
down to within the loop bandwidth. This is most likely to hap-
pen where the resolver is situated in particularly noisy environ-
ments, and the user is advised to fit a simple HF filter R1, C2
prior to the phase sensitive demodulator.
The attenuation and frequency response of a filter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. The suggested filter (R1, C1, R2, C2) is shown
in Figure 1 and gives an attenuation at the reference frequency
(fREF) of 3 times at the input to the phase sensitive demodulator.
Values of components used in the filter must be chosen to en-
sure that the phase shift at fREF is within the allowable signal to
reference phase shift of the converter.
Phase Sensitive Demodulator
The phase sensitive demodulator is effectively ideal and devel-
ops a mean dc output at the DEMODULATOR O/P pin of
rms voltage)
for sinusoidal signals in phase or antiphase with the reference
(for a square wave the DEMODULATOR O/P voltage will
equal the DEMODULATOR I/P). This provides a signal at the
DEMODULATOR O/P which is a dc level proportional to the
positional error of the converter.
DC Error Scaling = 160 mV/bit (10-bits resolution)
= 40 mV/bit (12-bits resolution)
= 10 mV/bit (14-bits resolution)
= 2.5 mV/bit (16-bits resolution)
When the tracking loop is closed, this error is nulled to zero
unless the converter input angle is accelerating.
The integrator components (R4, C4, R5, C5) are external to
the AD2S81A/AD2S82A to allow the user to determine the
optimum dynamic characteristics for any given application. The
Component Selection section explains how to select compo-
nents for a chosen bandwidth.
Since the output from the integrator is fed to the VCO INPUT,
it is proportional to velocity (rate of change of output angle)
and can be scaled by selection of R6, the VCO input resistor.
This is explained in the Voltage Controlled Oscillator (VCO)
section below.
To prevent the converter from “flickering” (i.e., continually
toggling by ±1 bit when the quantized digital angle, φ, is not an
exact representation of the input angle, θ), feedback is internally
applied from the VCO to the integrator input to ensure that the
VCO will only update the counter when the error is greater than
or equal to 1 LSB. In order to ensure that this feedback “hyster-
esis” is set to 1 LSB the input current to the integrator must be
scaled to be 100 nA/bit. Therefore,
R4 = DC Error Scaling (mV /bit )
100 (nA /bit )
Any offset at the input of the integrator will affect the accuracy
of the conversion as it will be treated as an error signal and
offset the digital output. One LSB of extra error will be
added for each 100 nA of input bias current. The method of
adjusting out this offset is given in the Component Selection
Voltage Controlled Oscillator (VCO)
The VCO is essentially a simple integrator feeding a pair of dc
level comparators. Whenever the integrator output reaches one
of the comparator threshold voltages, a fixed charge is injected
into the integrator input to balance the input current. At the
same time the counter is clocking either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the VCO.
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