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AD2S80A View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
AD2S80A Variable Resolution, Monolithic Resolver-to-Digital Converter ADI
Analog Devices ADI
AD2S80A Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD2S80A
CONNECTING THE CONVERTER
The power supply voltages connected to +VS and –VS pins
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to VL can be 5 V dc to +VS.
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +VS, –VS and ANALOG
GROUND adjacent to the converter. Recommended values
are 100 nF (ceramic) and 10 µF (tantalum). Also capacitors of
100 nF and 10 µF should be connected between +VL and
DIGITAL GROUND adjacent to the converter.
When more than one converter is used on a card, then separate
decoupling capacitors should be used for each converter.
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
shown in Figure 7 and described in section “CONNECTING
THE RESOLVER.”
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the converter to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
SIGNAL GROUND and ANALOG GROUND are connected
internally. ANALOG GROUND and DIGITAL GROUND
must be connected externally.
The external components required should be connected as
shown in Figure 1.
CONVERTER RESOLUTION
Two major areas of the AD2S80A specification can be selected
by the user to optimize the total system performance. The reso-
lution of the digital output is set by the logic state of the inputs
SC1 and SC2 to be 10, 12, 14, or 16 bits; and the dynamic
characteristics of bandwidth and tracking rate are selected by the
choice of external components.
The choice of the resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO respectively
(see section COMPONENT SELECTION). If the resolution is
changed, then new values of R4 and R6 must be switched into
the circuit.
Note: When changing resolution under dynamic conditions, do
it when the BUSY is low, i.e., when Data is not changing.
REFERENCE
I/P
HF FILTER
C3
R2
C1
R3
C2
R1
OFFSET ADJUST
R9
+12V
12V
R8
BANDWIDTH
SELECTION
R4
SIN
SIG GND
COS
GND
RIPPLE
CLK
+12V
12V
A1
SEGMENT
SWITCHING
A2
AC ERROR O/P
DEMOD
I/P
R-2R DAC
A3
PHASE
SENSITIVE
DETECTOR
AD2S80A
DEMOD
O/P
INTEGRATOR
I/P
INTEGRATOR
O/P
C5
C4
R5
VELOCITY
SIGNAL
16-BIT UP/DOWN COUNTER
OUTPUT DATA LATCH
VCO + DATA
TRANSFER LOGIC
R6
TRACKING
RATE
SELECTION
VCO
I/P
R7
C6
DATA SC1 SC2
LOAD
ENABLE
16 DATA BITS
BYTE 5V DIG BUSY DIRN INHIBIT
SELECT
GND
Figure 1. AD2S80A Connection Diagram
–6–
REV. B
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