AD1833ACST-REEL View Datasheet(PDF) - Analog Devices
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AD1833ACST-REEL Datasheet PDF : 20 Pages
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AD1833A
Address Reserved1
15–12 11 10
0000 0
0
De-emphasis
9–8
00 = None
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
NOTES
1Must be programmed to zero.
2For IMCLK = 24.576 MHz.
Table II. DAC Control Register 1
Serial Mode
7–5
000 = I2S
001 = RJ
010 = DSP
011 = LJ
100 = Pack Mode 1 (256)
101 = Pack Mode 2 (128)
110 = TDM Mode
111 = Reserved
Function
Data-Word
Width
4–3
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
Power-Down
RESET
2
0 = Normal
1 = PWRDWN
Interpolator
Mode
1–0
00 = 8ϫ (48 kHz)2
01 = 2ϫ (192 kHz)2
10 = 4ϫ (96 kHz)2
11 = Reserved
DAC CONTROL REGISTER 1
De-emphasis
The AD1833A has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
Redbook 50 ms/15 ms emphasis response curve. Three curves are
available, one each for 32 kHz, 44.1 kHz, and 48 kHz sampling
rates. The filters may be selected by writing to Control Bits 9
and 8 in DAC Control Register 1 (see Table III).
Table III. De-emphasis Settings
Bit 9
Bit 8
De-emphasis
0
0
0
1
1
0
1
1
Disabled
44.1 kHz
32 kHz
48 kHz
Data Serial Interface Mode
The AD1833A’s serial data interface is designed to accept data
in a wide range of popular formats including I2S, right-justified
(RJ), left-justified (LJ), and flexible DSP modes. The L/RCLK
pin acts as the word clock (or frame sync) to indicate sample
interval boundaries. The BCLK defines the serial data rate
while the data is input on the SDIN1–SDIN3 pins. The serial
mode settings may be selected by writing to Control Bits 7
through 5 in the DAC Control Register 1 (see Table IV).
Table IV. Data Serial Interface Mode Settings
Bit 7
0
0
0
0
1
1
1
1
Bit 6
0
0
1
1
0
0
1
1
Bit 5
0
1
0
1
0
1
0
1
Serial Mode
I2S
Right Justify
DSP
Left Justify
Packed Mode 1 (256)
Packed Mode 2 (128)
TDM Mode
Reserved
DAC Word Width
The AD1833A will accept input data in three separate word-
lengths—16 bits, 20 bits, and 24 bits. The word length may be
selected by writing to Control Bits 4 and 3 in DAC Control
Register 1 (see Table V).
Table V. Word Length Settings
Bit 4
0
0
1
1
Bit 3
0
1
0
1
Word Length
24 Bits
20 Bits
16 Bits
Reserved
Power-Down Control
The AD1833A can be powered down by writing to Control Bit 2
in DAC Control Register 1 (see Table VI).
Table VI. Power-Down Control
Bit 2
0
1
Power-Down Setting
Normal Operation
Power-Down Mode
Interpolator Mode
The AD1833A’s DAC interpolators can be operated in one of
three modes—8ϫ, 4ϫ, or 2ϫ— then correspond to 48 kHz, 96 kHz,
and 192 kHz modes, respectively (for IMCLK = 24.576 MHz). The
interpolator mode may be selected by writing to Control Bits 1
and 0 in DAC Control Register 1 (see Table VII).
Table VII. Interpolator Mode Settings
Bit 1
Bit 0
0
0
0
1
1
0
1
1
*For IMCLK = 24.576 MHz.
Interpolator Mode
8x (48 kHz)*
2x (192 kHz)*
4x (96 kHz)*
Reserved
REV. 0
–11–
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