AD1819B View Datasheet(PDF) - Analog Devices
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Description
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AD1819B Datasheet PDF : 28 Pages
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AD1819B
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Start-Up Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Start-Up Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to
SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
tSYNC_PERIOD
tSETUP
tHOLD
tRISE CLK
tFALL CLK
tRISE SYNC
tFALL SYNC
tRISE DIN
tFALL DIN
tRISE DOUT
tFALL DOUT
tS2_PDOWN
tSETUP2RST
tOFF
1.0
162.8
0.0814
162.8
32.56
32.56
15.0
15.0
15
1.3
19.5
12.288
81.4
40.7
40.7
48.0
20.8
4
4
4
4
4
4
4
4
*Output Jitter is directly dependent on crystal input jitter.
RESET
BIT_CLK
tRST_LOW
tRST2CLK
Figure 1. Cold Reset
Max
750
48.84
48.84
1.0
25
SYNC
BIT_CLK
tSYNC_HIGH
tRST2CLK
Figure 2. Warm Reset
BIT_CLK
SYNC
tCLK_LOW
tCLK_HIGH
tCLK_PERIOD
tSYNC_LOW
tSYNC_HIGH
tSYNC_PERIOD
Figure 3. Clock Timing
Units
µs
ns
µs
µs
ns
MHz
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
–6–
REV. 0
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