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ACT8891 View Datasheet(PDF) - Active-Semi, Inc

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ACT8891 Datasheet PDF : 30 Pages
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ACT8891
Rev 1, 06-Sep-13
REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
OUTPUT ADDRESS BIT NAME ACCESS
DESCRIPTION
SYS
0x00 [7]
TRST
Reset Timer Setting. Defines the reset time-out threshold. Reset
R/W time-out is 65ms when value is 1, reset time-out is 260ms when
value is 0. See nRSTO Output section for more information.
SYS
0x00
[6] nSYSMODE
R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Generate an interrupt when VVDDREF falls
below the programmed SYSLEV threshold, 0: automatic
shutdown when VVDDREF falls below the programmed SYSLEV
threshold.
SYS
0x00
[5] nSYSLEVMSK R/W
System Voltage Level Interrupt Mask. Disabled interrupt by
default, set to 1 to enable this interrupt. See the Programmable
System Voltage Monitor section for more information
SYS
0x00 [4] nSYSSTAT
System Voltage Status. Value is 1 when VVDDREF is lower than the
R SYSLEV voltage threshold, value is 0 when VVDDREF is higher
than the system voltage detection threshold.
SYS
0x00 [3:0] SYSLEV
System Voltage Detect Threshold. Defines the SYSLEV voltage
R/W threshold. See the Programmable System Voltage Monitor
section for more information.
SYS
0x01 [7:4]
-
R/W Reserved.
SYS
0x01 [3:0] SCRATCH
Scratchpad Bits. Non-functional bits, maybe be used by user to
R/W store system status information. Volatile bits, which are cleared
upon system shutdown.
REG1 0x20 [7:6]
-
R Reserved.
REG1 0x20 [5:0] VSET1
Primary Output Voltage Selection. Valid when VSEL is driven low.
R/W See the Output Voltage Programming section for more
information.
REG1 0x21 [7:6]
-
R Reserved.
REG1 0x21 [5:0] VSET2
Secondary Output Voltage Selection. Valid when VSEL is driven
R/W high. See the Output Voltage Programming section for more
information.
REG1 0x22 [7]
ON
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit
to 0 to disable the regulator.
REG1 0x22 [6] PHASE
Regulator Phase Control. Set bit to 1 for regulator to operate
R/W 180° out of phase with the oscillator, clear bit to 0 for regulator to
operate in phase with the oscillator.
REG1 0x22 [5]
MODE
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
R/W under all load conditions, clear bit to 0 to transit to power-savings
mode under light-load conditions.
REG1 0x22 [4:2] DELAY
R/W
Regulator Turn-On Delay Control. See the REG1, REG2, REG3
Turn-on Delay section for more information.
REG1
0x22
[1] nFLTMSK
R/W
Regulator Fault Mask Control. Set bit to 1 enable to fault-
interrupts, clear bit to 0 to disable fault-interrupts.
REG1 0x22 [0]
OK
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
REG2 0x30 [7:6]
-
R Reserved.
REG2 0x30 [5:0] VSET1
Primary Output Voltage Selection. Valid when VSEL is driven low.
R/W See the Output Voltage Programming section for more
information.
REG2 0x31 [7:6]
-
R Reserved.
REG2 0x31 [5:0] VSET2
Secondary Output Voltage Selection. Valid when VSEL is driven
R/W high. See the Output Voltage Programming section for more
information.
Innovative PowerTM
- 10 -
Active-Semi ProprietaryFor Authorized Recipients and Customers
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
 

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