datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

P83C552IFB View Datasheet(PDF) - Philips Electronics

Part Name
Description
View to exact match
P83C552IFB Datasheet PDF : 23 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
Philips Semiconductors
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
Product data
80C552/83C552
VDD
P1.6
P1.7
VDD
(NC)
CLOCK SIGNAL
RST
STADC
XTAL2
XTAL1
VSS
VDD
IDD
VDD
VDD
P0
EA
EW
AVSS
AVref–
VDD–0.5
0.5 V
0.7VDD
0.2VDD–0.1
tCHCL
tCLCX
tCHCX
tCLCH
tCLCL
SU01704
Figure 12. IDD Test Condition, Active Mode
All other pins are disconnected1
VDD
P1.6
P1.7
RST
STADC
VDD
IDD
VDD
VDD
P0
(NC)
CLOCK SIGNAL
XTAL2
XTAL1
VSS
EW
EA
AVSS
AVref–
SU01706
Figure 14. Clock Signal Waveform for IDD Tests in Active and
Idle Modes tCLCH = tCHCL = 5ns
VDD
P1.6
P1.7
RST
STADC
IDD
VDD
VDD
VDD
P0
(NC)
XTAL2
XTAL1
VSS
EW
EA
AVSS
AVref–
SU01705
SU01707
Figure 13. IDD Test Condition, Idle Mode
All other pins are disconnected2
NOTES:
Figure 15. IDD Test Condition, Power Down Mode
All other pins are disconnected. VDD = 2 V to 5.5 V3
1. Active Mode:
a. The following pins must be forced to VDD: EA, RST, Port 0, and EW.
b. The following pins must be forced to VSS: STADC, AVss, and AVref–.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2. Idle Mode:
a. The following pins must be forced to VDD: Port 0 and EW.
b. The following pins must be forced to VSS: RST, STADC, AVss,, AVref–, and EA.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
3. Power Down Mode:
a. The following pins must be forced to VDD: Port 0 and EW.
b. The following pins must be forced to VSS: RST, STADC, XTAL1, AVss,, AVref–, and EA.
c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2002 Sep 03
20
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]