P83C552IFB View Datasheet(PDF) - Philips Electronics
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Description
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P83C552IFB
Philips Electronics
P83C552IFB Datasheet PDF : 23 Pages
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Philips Semiconductors
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
Product data
80C552/83C552
AC ELECTRICAL CHARACTERISTICS (Continued)1, 2
24 MHz version
24 MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN
MAX
1/tCLCL
2
tLHLL
2
tAVLL
2
tLLAX
2
tLLIV
2
tLLPL
2
tPLPH
2
tPLIV
2
tPXIX
2
tPXIZ
2
tAVIV
2
tPLAZ
2
Data Memory
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
3.5
24
43
2tCLCL–40
17
tCLCL–25
17
tCLCL–25
102
4tCLCL–65
17
tCLCL–25
80
3tCLCL–45
65
3tCLCL–60
0
0
17
tCLCL–25
128
5tCLCL–80
10
10
tRLRH
3
RD pulse width
150
6tCLCL–100
tWLWH
4
WR pulse width
150
6tCLCL–100
tRLDV
3
RD low to valid data in
118
5tCLCL–90
tRHDX
3
Data hold after RD
0
0
tRHDZ
3
Data float after RDxs
55
2tCLCL–28
tLLDV
3
ALE low to valid data in
183
8tCLCL–150
tAVDV
3
Address to valid data in
210
9tCLCL–165
tLLWL
3, 4
ALE low to RD or WR low
75
175
3tCLCL–50
3tCLCL+50
tAVWL
3, 4
Address valid to WR low or RD low
92
4tCLCL–75
tQVWX
4
Data valid to WR transition
12
tCLCL–30
tDW
4
Data before WR
162
7tCLCL–130
tWHQX
4
Data hold after WR
17
tCLCL–25
tRLAZ
3
RD low to address float
0
0
tWHLH
3, 4
RD or WR high to ALE high
17
67
tCLCL–25
tCLCL+25
External Clock
tCHCX
5
High time3
17
17
tCLCX
5
Low time3
17
17
tCLCH
5
Rise time3
5
20
tCHCL
5
Fall time3
5
20
Serial Timing – Shift Register Mode3 (Test Conditions: Tamb = 0 °C to +70 °C; VSS = 0 V; Load Capacitance = 80 pF)
tXLXL
6
Serial port clock cycle time
0.5
12tCLCL
tQVXH
6
Output data setup to clock rising edge
283
10tCLCL–133
tXHQX
6
Output data hold after clock rising edge
23
2tCLCL–60
tXHDX
6
Input data hold after clock rising edge
0
0
tXHDV
6
Clock rising edge to input data valid
283
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.
4. tCLCL = 1/fOSC = one oscillator clock period.
tCLCL = 41.7ns at fOSC = 24 MHz.
10tCLCL–133
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
2002 Sep 03
14
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