ACPL-K73L-060E View Datasheet(PDF) - Avago Technologies

Part Name

Description

View to exact match

ACPL-K73L-060E

Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature

Avago Technologies 

Switching Specifications

Over recommended temperature (TA = –40°C to +105°C), 3.0V≤VDD ≤ 3.6V and 4.5 V ≤VDD ≤ 5.5 V.

All typical specifications are at TA=+25°C, VDD = +3.3V.

Parameter

Propagation Delay Time

to Logic Low Output[2]

Propagation Delay Time

to Logic High Output[2]

Pulse Width

Pulse Width Distortion[3]

Symbol

tPHL

tPLH

tPW

|PWD|

Propagation Delay Skew[4]

tPSK

Output Rise Time

(10% – 90%)

Output Fall Time

(90% - 10%)

Common Mode Transient Immunity

at Logic High Output[5]

Common Mode Transient Immunity

at Logic Low Output[6]

tR

tF

| CMH |

| CML |

Min. Typ. Max. Units Test Conditions

23

55

ns

IF = 6 mA, CL= 15pF

CMOS Signal Levels

27

55

ns

IF = 6 mA, CL= 15pF

CMOS Signal Levels

66.7

ns

0

4

25

ns

IF = 6 mA, CL= 15pF

CMOS Signal Levels

40

ns

IF = 6 mA, CL= 15pF

CMOS Signal Levels

3.5

ns

IF = 6 mA, CL= 15pF

CMOS Signal Levels

3.5

ns

IF = 0 mA, CL= 15pF

CMOS Signal Levels

10

15

kV/µs VCM = 1000 V, TA = 25°C, IF = 6 mA

10

15

kV/µs VCM = 1000 V, TA = 25°C, IF = 0 mA

Package Characteristics

All Typical at TA = 25°C.

Parameter

Symbol

Min. Typ. Max. Units Test Conditions

Input-Output Insulation

II-O

1.0

µA

45% RH, t = 5 s

VI-O = 3 kV DC,

TA = 25°C

Input-Output Momentary

Withstand Voltage

Input-Output Resistance

VISO

5000

R I-O

10 12

Vrms RH ≤ 50%, t = 1 min.,

TA = 25°C

W

V I-O = 500 V dc

Input-Output Capacitance

C I-O

0.6

pF

f = 1 MHz, TA = 25°C

Notes:

1. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin.

2. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level on the falling edge of the VO signal.

tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level on the rising edge of the VO signal.

3. PWD is defined as |tPHL - tPLH|.

4. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the

recommended operating conditions.

5. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.

6. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.

7

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