A8904SLB View Datasheet(PDF) - Allegro MicroSystems

Part Name

Description

View to exact match

A8904SLB

3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING

Allegro MicroSystems 

8904

3-PHASE BRUSHLESS DC

MOTOR CONTROLLER/DRIVER

Functional Description (cont’d)

If the motor moves, the back-EMF detection and direction

circuit waits for the correct polarity of back-EMF zero crossing

(output crossing through centertap). If the correct polarity of

back-EMF is not detected, a watchdog circuit commutates the

output until the correct back-EMF is detected. Correct back-

EMF sensing is indicated by the FCOM signal, which toggles

every time the back-EMF completes a zero crossing (see

waveforms below). FCOM is available at the DATA OUT

terminal.

True back-EMF zero crossings are used by the adaptive

commutation delay circuit to advance the state sequencer

(commutate) at the proper time to synchronously run the motor.

See next section.

Adaptive commutation delay. The adaptive commuta-

tion delay circuit uses the back-EMF zero-crossing indicator

signal (FCOM) to determine an optimal commutation time for

efficient synchronous switching of the output drivers. When the

FCOM signal changes state, one of the delay capacitors (CD1 or

CD2) is discharged at approximately twice the rate of the

charging current. When the capacitor reaches the 2.5 V thresh-

old, a commutation occurs. During this discharge period, the

other delay capacitor is being charged in anticipation of the next

FCOM state change. In addition, there is an interruption to the

charging, which is set by the blanking duration (see waveform

below, VCWD, and next section). This additional charging delay

causes the commutation to occur at slightly less than 50% of the

FCOM on or off duration, to compensate for delays caused by

winding inductance.

The typical delta voltage change during normal operation in

the commutation capacitors (CD1 & CD2), will range between

1.5 V and 2.0 V. The commutation capacitor values can be

determined from:

CDX = ICD x t / VCD

where VCD = 1.5 V, ICD = 20 µA, and t = (60/rpm)/(#motor

poles x 3), duration of each state.

To avoid the capacitors charging to the supply rail, the value

selected should provide adequate margin, taking into account the

effects of capacitor tolerance, charging current, etc.

Blanking and watchdog timing functions. The

blanking and watchdog timing functions are derived from one

timing capacitor CWD .

During normal commutation, at the beginning of each new

sequencer state, a blanking signal is created until the watchdog

capacitor CWD is charged to the threshold VTL (see waveforms

below). This blanking signal prohibits the back-EMF compara-

tors from tripping due to the discharging of inductive energy and

voltage settling transients during sequence state transitions. The

duration of this blanking signal depends on the size of the CWD

capacitor and the programmed charge current, ICWD (via D26-

27). This blanking pulse also interrupts the commutation delay

capacitors CD1 and CD2 from charging (see previous section).

The ability to select the minimum charge current for CWD is

particularly useful during start-up, where the duration of the

diode recirculation current is highest. In applications where

high motor speeds are experienced, the charge current can be

increased so that the blanking period does not encroach signifi-

cantly into the period of each sequencer state and does not cause

www.allegromicro.com

9

Share Link: