A8904SLB View Datasheet(PDF) - Allegro MicroSystems
Part Name
Description
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A8904SLB Datasheet PDF : 19 Pages
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8904
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Terminal Functions
Terminal Name
Function
LOAD SUPPLY
CD2
VBB; the 5 V or 12 V motor supply.
One of two capacitors used to generate the ideal commutation points from
the back-EMF zero crossing points.
CWD
Timing capacitor used by the watchdog circuit to blank out the back-EMF
comparators during commutation transients, and to detect incorrect motor
position.
CST
Startup oscillator timing capacitor.
NC
No( internal) connection.
OUTA
NC
Power amplifier A output to motor.
No (internal) connection.
GROUND
Power and logic ground and thermal heat sink.
POWER GROUND Power ground.
NC
No (internal) connection.
OUTB
OUTC
CENTERTAP
Power amplifier B output to motor.
Power amplifier C output to motor.
Motor centertap connection for back-EMF detection circuitry.
BRAKE
Active low turns ON all three sink drivers shorting the motor windings to
ground. External capacitor and resistor at BRAKE provide brake delay.
The brake function can also be controlled via the serial port.
CRES
External reservoir capacitor used to hold charge to drive the source drivers’
gates. Also provides power for brake circuit.
ANALOG GROUND Analog ground.
FILTER
Analog voltage input/output to control motor current. Also, compensation node
for internal speed control loop.
SECTOR DATA
External tachometer input. Can use sector or index pulses from disk to
provide precise motor speed feedback to internal frequency-locked loop.
LOGIC SUPPLY
OSCILLATOR
VDD; the 5 V logic supply.
Clock input for the speed reference counter.
DATA OUT
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in
real time, controlled by 2-bit multiplexer via serial port.
NC
No (internal) connection.
GROUND
Power and logic ground and thermal heat sink.
DIGITAL GROUND Logic ground.
RESET
NC
When pulled low forces the chip into sleep mode; clears all serial port bits.
No (internal) connection.
CHIP SELECT
CLOCK
Strobe input (active low) for data word.
Clock input for serial port.
DATA IN
Sequential data input for the serial port.
CD1
One of two capacitors used to generate the ideal commutation points from
the back-EMF zero crossing points.
* For the A8904SLP, ground terminals 1, 8, and 22 must be connected together externally.
A8904SLB
(SOIC)
1
2
3
4
–
5
–
6-7
–
–
8
9
10
11
12
–
13
14
15
16
17
–
18-19
–
20
–
21
22
23
24
A8904SLP
(TSSOP)
15
16
17
18
19
20
21
–
22*
23
24
25
26
27
28
1*
2
3
4
5
6
7
–
8*
9
10
11
12
13
14
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