datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

93AA56CT-EMSG View Datasheet(PDF) - Microchip Technology

Part Name
Description
View to exact match
93AA56CT-EMSG
Microchip
Microchip Technology Microchip
93AA56CT-EMSG Datasheet PDF : 0 Pages
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.5 ERASE ALL (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
VCC must be 4.5V for proper operation of ERAL.
FIGURE 2-3:
CS
ERAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CHECK STATUS
CLK
DI
1
0
0
1
0
X •••
X
HIGH-Z
DO
VCC must be 4.5V for proper operation of ERAL.
FIGURE 2-4:
CS
ERAL TIMING FOR 93C DEVICES
TCSL
TSV
BUSY
TEC
TCZ
READY
HIGH-Z
CHECK STATUS
CLK
DI
1
0
0
1
0
X •••
X
HIGH-Z
DO
TSV
BUSY
TEC
TCZ
READY
HIGH-Z
2003 Microchip Technology Inc.
DS21794B-page 7
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]