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93AA56CT-ISTG View Datasheet(PDF) - Microchip Technology

Part Name
Description
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93AA56CT-ISTG
Microchip
Microchip Technology Microchip
93AA56CT-ISTG Datasheet PDF : 0 Pages
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.9 WRITE ALL (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA56A/B/C and 93LC56A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C56A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
VCC must be 4.5V for proper operation of WRAL.
FIGURE 2-10:
CS
WRAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
CLK
DI
1
0
0
0
1
X ••• X Dx ••• D0
HIGH-Z
DO
VCC must be 4.5V for proper operation of WRAL.
TSV
TCZ
BUSY
TWL
READY
HIGH-Z
FIGURE 2-11:
WRAL TIMING FOR 93C DEVICES
TCSL
CS
CLK
DI
1
0
0
0
1
X ••• X Dx ••• D0
TSV
TCZ
HIGH-Z
DO
BUSY READY
HIGH-Z
TWL
DS21794B-page 10
2003 Microchip Technology Inc.
 

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