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80C32EBPN View Datasheet(PDF) - Philips Electronics

Part Name
Description
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80C32EBPN
Philips
Philips Electronics Philips
80C32EBPN Datasheet PDF : 62 Pages
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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C52/80C54/80C58
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
24MHz CLOCK
VARIABLE CLOCK4
33MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
MIN MAX UNIT
1/tCLCL
13
Oscillator frequency
3.5
Speed versions : I (24MHz)
3.5
24
: N (33MHz)
33
MHz
3.5
33
tLHLL
13
tAVLL
13
tLLAX
13
tLLIV
13
tLLPL
13
tPLPH
13
tPLIV
13
tPXIX
13
tPXIZ
13
tAVIV
13
tPLAZ
13
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
43
2tCLCL–40
21
ns
17
tCLCL–25
5
ns
17
tCLCL–25
ns
102
4tCLCL–65
55
ns
17
tCLCL–25
5
ns
80
3tCLCL–45
45
ns
65
3tCLCL–60
30
ns
0
0
0
ns
17
tCLCL–25
5
ns
128
5tCLCL–80
70
ns
10
10
10
ns
tRLRH
14, 15
tWLWH
14, 15
tRLDV
14, 15
tRHDX
14, 15
tRHDZ
14, 15
tLLDV
14, 15
tAVDV
14, 15
tLLWL
14, 15
tAVWL
14, 15
tQVWX
14, 15
tWHQX
14, 15
tQVWH
15
tRLAZ
14, 15
tWHLH
14, 15
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
150
6tCLCL–100
82
ns
150
6tCLCL–100
82
ns
118
5tCLCL–90
60
ns
0
0
0
ns
55
2tCLCL–28
32
ns
183
8tCLCL–150
90
ns
210
9tCLCL–165
105 ns
75
175 3tCLCL–50 3tCLCL+50
40
140
ns
92
4tCLCL–75
45
ns
12
tCLCL–30
0
ns
17
tCLCL–25
5
ns
162
7tCLCL–130
80
ns
0
0
0
ns
17
67
tCLCL–25
tCLCL+25
5
55
ns
tCHCX
17
tCLCX
17
tCLCH
17
tCHCL
17
Shift Register
High time
Low time
Rise time
Fall time
17
17
tCLCL–tCLCX
ns
17
17
tCLCL–tCHCX
ns
5
5
ns
5
5
ns
tXLXL
16
Serial port clock cycle time
505
12tCLCL
360
ns
tQVXH
16
Output data setup to clock rising edge 283
10tCLCL–133
167
ns
tXHQX
16
Output data hold after clock rising edge 3
2tCLCL–80
ns
tXHDX
16
Input data hold after clock rising edge
0
0
0
ns
tXHDV
16
Clock rising edge to input data valid
283
10tCLCL–133
167 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
“AC Electrial Characteristics”, page 20.
1996 Aug 16
21
 

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