80C32EFAA View Datasheet(PDF) - Philips Electronics
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80C32EFAA Datasheet PDF : 62 Pages
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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C52/80C54/80C58
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
16MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
UNIT
1/tCLCL
13
Oscillator frequency
Speed versions : E
3.5
16
MHz
tLHLL
13
tAVLL
13
tLLAX
13
tLLIV
13
tLLPL
13
tPLPH
13
tPLIV
13
tPXIX
13
tPXIZ
13
tAVIV
13
tPLAZ
13
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in4
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in4
PSEN low to address float
85
2tCLCL–40
ns
22
tCLCL–40
ns
32
tCLCL–30
ns
150
4tCLCL–100
ns
32
tCLCL–30
ns
142
3tCLCL–45
ns
82
3tCLCL–105
ns
0
0
ns
37
tCLCL–25
ns
207
5tCLCL–105
ns
10
10
ns
tRLRH
14, 15
tWLWH
14, 15
tRLDV
14, 15
tRHDX
14, 15
tRHDZ
14, 15
tLLDV
14, 15
tAVDV
14, 15
tLLWL
14, 15
tAVWL
14, 15
tQVWX
14, 15
tWHQX
14, 15
tQVWH
15
tRLAZ
14, 15
tWHLH
14, 15
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
275
6tCLCL–100
ns
275
6tCLCL–100
ns
147
5tCLCL–165
ns
0
0
ns
65
2tCLCL–60
ns
350
8tCLCL–150
ns
397
9tCLCL–165
ns
137 239
3tCLCL–50
3tCLCL+50
ns
122
4tCLCL–130
ns
13
tCLCL–50
ns
13
tCLCL–50
ns
287
7tCLCL–150
ns
0
0
ns
23
103
tCLCL–40
tCLCL+40
ns
tCHCX
17
tCLCX
17
tCLCH
17
tCHCL
17
Shift Register
High time
Low time
Rise time
Fall time
20
20
tCLCL–tCLCX
ns
20
20
tCLCL–tCHCX
ns
20
20
ns
20
20
ns
tXLXL
16
Serial port clock cycle time
750
12tCLCL
ns
tQVXH
16
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
16
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
16
Input data hold after clock rising edge
0
0
ns
tXHDV
16
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interfacing.
1996 Aug 16
20
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