P80C32EFBB View Datasheet(PDF) - Philips Electronics
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P80C32EFBB Datasheet PDF : 62 Pages
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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C32/87C52
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 4.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.
DESIGN CONSIDERATIONS
At power-on, the voltage on VCC and RST must come up at the
same time for a proper start-up.
Table 5 shows the state of I/O ports during low current operating
modes.
As a precaution to coming out of an unexpected power down, INT0
and INT1 should be disabled prior to enterring power down.
Table 5. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
Idle
Internal
1
1
Data
Idle
External
1
1
Float
Power-down
Internal
0
0
Data
Power-down
External
0
0
Float
PORT 1
Data
Data
Data
Data
PORT 2
Data
Address
Data
Data
PORT 3
Data
Data
Data
Data
1996 Aug 16
12
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