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80C32E View Datasheet(PDF) - Philips Electronics

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80C32E
Philips
Philips Electronics Philips
80C32E Datasheet PDF : 62 Pages
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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C52/80C54/80C58
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM0
SM1
SM2
REN
TB8
RB8
TI
1
1
1
0
1
1
X
RI
SCON
(98H)
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
SU00045
Interrupt Priority Structure
The 80C52/54/58 has a 6-source four-level interrupt structure. There
are 3 SFRs associated with the interrupts on the 80C52/54/58. They
are the IE and IP. (See Figures 10 and 11.) In addition, there is the
IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown below:
IPH (Interrupt Priority High) (B7H)
7
6
5
4
3
2
1
0
PT2H
PSH
PT1H PX1H PT0H PX0H
IPH.0
IPH.1
IPH.2
IPH.3
IPH.4
IPH.5
IPH.6
IPH.7
PX0H
PT0H
PX1H
PT1H
PSH
PT2H
External interrupt 0 priority high
Timer 0 interrupt priority high
External interrupt 1 priority high
Timer 1 interrupt priority high
Serial Port interrupt high
Timer 2 interrupt priority high
Not implemented
Not implemented
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
IPH.x
IP.x
0
0
0
1
1
0
1
1
INTERRUPT PRIORITY LEVEL
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels on the
80C52/54/58 rather than two as on the 80C51. An interrupt will be
serviced as long as an interrupt of equal or higher priority is not
already being serviced. If an interrupt of equal or higher level priority
is being serviced, the new interrupt will wait until it is finished before
being serviced. If a lower priority level interrupt is being serviced, it
will be stopped and the new interrupt serviced. When the new
interrupt is finished, the lower priority level interrupt that was
stopped will be completed.
Table 7. Interrupt Table
SOURCE
POLLING PRIORITY
X0
1
T0
2
X1
3
T1
4
SP
5
T2
6
PCA
7
NOTES:
1. L = Level activated
2. T = Transition activated
REQUEST BITS
IE0
TP0
IE1
TF1
R1, TI
TF2, EXF2
CF, CCFn
n = 0–4
HARDWARE CLEAR?
N (L)1 Y (T)2
Y
N (L) Y (T)
Y
N
N
N
VECTOR ADDRESS
03H
0BH
13H
1BH
23H
2BH
33H
1996 Aug 16
16
 

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