CMOS single-chip 8-bit microcontrollers
PIN DESCRIPTIONS (Continued)
MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION
P3.0–P3.7 10–17 11,
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51
family, as listed below:
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VCC.
O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
O Program Store Enable: The read strobe to external program memory. When the
80C52/80C54/80C58 is executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory. PSEN is not activated during fetches from internal
I External Access Enable: EA must be externally held low to enable the device to fetch code
from external program memory locations 0000H and 7FFFH. If EA is held high, the device
executes from internal program memory unless the program counter contains an address
greater than 7FFFH. If security bit 1 is programmed, EA will be internally latched on Reset.
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
O Crystal 2: Output from the inverting oscillator amplifier.
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS – 0.5V, respectively.
1996 Aug 16