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80C32E View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
80C32E CMOS single-chip 8-bit microcontrollers Philips
Philips Electronics Philips
80C32E Datasheet PDF : 62 Pages
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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
The 80C52/80C54/80C58 Single-Chip 8-Bit Microcontroller is
manufactured in an advanced CMOS process and is a derivative of
the 80C51 microcontroller family. The 80C52/80C54/80C58 has the
same instruction set as the 80C51.
This device provides architectural enhancements that make it
applicable in a variety of applications for general control systems.
The 80C52 contains 8k × 8 ROM memory, the 80C54 contains
16k × 8 ROM memory, and 80C58 contains 32k × 8 ROM memory, a
volatile 256 × 8 read/write data memory, four 8-bit I/O ports, three
16-bit timer/event counters, a multi-source, four-priority-level, nested
interrupt structure, an enhanced UART and on-chip oscillator and
timing circuits. For systems that require extra capability, the
80C52/54/58 can be expanded using standard TTL compatible
memories and logic.
Its added features make it an even more powerful microcontroller for
applications that require pulse width modulation, high-speed I/O and
up/down counting capabilities such as motor control. It also has a
more versatile serial channel that facilitates multiprocessor
See 87C52/80C32 and 87C54/87C58 data sheets for EPROM and
ROMless devices.
80C51 central processing unit
Full static operation
8k × 8 ROM: 80C52;
16k × 8 ROM: 80C54;
32k × 8 ROM: 80C58;
all capable of addressing external memory to 64k bytes
Two level program security system
64 byte encryption array
256 × 8 RAM, expandable externally to 64k bytes
Speed range up to 33MHz
Operating voltage 5V ±10%
Three 16-bit timer/counters
T2 is an up/down counter
6 interrupt sources
4 level priority
Four 8-bit I/O ports
Full-duplex enhanced UART
Framing error detection
Automatic address recognition
Power control modes
Idle mode
Power-down mode
Once (On Circuit Emulation) Mode
Five package styles
Programmable clock out
Low EMI (Inhibit ALE)
Second DPTR register
Asynchronous port reset
T2/P1.0 1
T2EX/P1.1 2
P1.2 3
P1.3 4
P1.4 5
P1.5 6
P1.6 7
P1.7 8
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
VSS 20
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
1996 Aug 16
853–1470 17196
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