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80C32E View Datasheet(PDF) - Philips Electronics

Part NameDescriptionManufacturer
80C32E CMOS single-chip 8-bit microcontrollers Philips
Philips Electronics Philips
80C32E Datasheet PDF : 62 Pages
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Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C32/87C52
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3
24MHz CLOCK
VARIABLE CLOCK
33MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN MAX
MIN
MAX
MIN MAX UNIT
1/tCLCL
5
Oscillator frequency
Speed versions : I
:N
3.5
24
MHz
3.5
33
tLHLL
5
tAVLL
5
tLLAX
5
tLLIV
5
tLLPL
5
tPLPH
5
tPLIV
5
tPXIX
5
tPXIZ
5
tAVIV
5
tPLAZ
5
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
43
2tCLCL–40
21
ns
17
tCLCL–25
5
ns
17
tCLCL–25
5
ns
102
4tCLCL–65
56
ns
17
tCLCL–25
5
ns
80
3tCLCL–45
46
ns
65
3tCLCL–60
31
ns
0
0
0
ns
17
tCLCL–25
5
ns
128
5tCLCL–80
72
ns
10
10
10
ns
tRLRH
6, 7
tWLWH
6, 7
tRLDV
6, 7
tRHDX
6, 7
tRHDZ
6, 7
tLLDV
6, 7
tAVDV
6, 7
tLLWL
6, 7
tAVWL
6, 7
tQVWX
6, 7
tWHQX
6, 7
tQVWH
7
tRLAZ
6, 7
tWHLH
6, 7
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
150
6tCLCL–100
82
ns
150
6tCLCL–100
82
ns
118
5tCLCL–90
62
ns
0
0
0
ns
55
2tCLCL–28
33
ns
183
8tCLCL–150
92
ns
210
9tCLCL–165
108
ns
75
175 3tCLCL–50 3tCLCL+50
41
141
ns
92
4tCLCL–75
46
ns
12
tCLCL–30
0.3
ns
17
tCLCL–25
5
ns
162
7tCLCL–130
82
ns
0
0
0
ns
17
67
tCLCL–25
tCLCL+25
5
5
ns
tCHCX
9
tCLCX
9
tCLCH
9
tCHCL
9
Shift Register
High time
Low time
Rise time
Fall time
17
17
tCLCL–tCLCX
ns
17
17
tCLCL–tCHCX
ns
5
5
ns
5
5
ns
tXLXL
8
Serial port clock cycle time
505
12tCLCL
363
ns
tQVXH
8
Output data setup to clock rising edge 283
10tCLCL–133
170
ns
tXHQX
8
Output data hold after clock rising edge 3
2tCLCL–80
19
ns
tXHDX
8
Input data hold after clock rising edge
0
0
0
ns
tXHDV
8
Clock rising edge to input data valid
283
10tCLCL–133
170
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 8XC52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
“AC Electrial Characteristics”, page 15.
1996 Aug 16
16
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