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74VCXH16240DTR-2000 View Datasheet(PDF) - ON Semiconductor

Part NameDescriptionManufacturer
74VCXH16240DTR(2000) Low−Voltage 1.8/2.5/3.3V 16−Bit Buffer ON-Semiconductor
ON Semiconductor ON-Semiconductor
74VCXH16240DTR Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
K
t
TOP
COVER
TAPE
B1
K0
SEE
NOTE 2
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B0
74VCXH16240
10 PITCHES
CUMULATIVE
TOLERANCE ON
P0
TAPE
±0.2 mm
D
P2
(±0.008")
E
A0 SEE NOTE 2
+ B0
+
P
EMBOSSMENT
USER DIRECTION OF FEED
FW
+
CENTER LINES
OF CAVITY
D1
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
BENDING RADIUS
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
*TOP COVER
TAPE THICKNESS (t1)
0.10 mm
(0.004") MAX.
EMBOSSMENT
10°
MAXIMUM COMPONENT ROTATION
TYPICAL
COMPONENT CAVITY
CENTER LINE
100 mm
(3.937")
1 mm MAX
TAPE
TYPICAL
COMPONENT
CENTER LINE
1 mm
(0.039") MAX
250 mm
(9.843")
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 7. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape
Size
B1
Max
D
D1
E
F
K
P
P0
P2
R
T
W
24mm
20.1mm
(0.791")
1.5 + 0.1mm
-0.0
(0.059
+0.004" -0.0)
1.5mm
Min
(0.060")
1.75
±0.1 mm
(0.069
±0.004")
11.5
±0.10 mm
(0.453
±0.004")
11.9 mm
Max
(0.468")
16.0
±0.1 mm
(0.63
±0.004")
4.0
±0.1 mm
(0.157
±0.004")
2.0
±0.1 mm
(0.079
±0.004")
30 mm
(1.18")
0.6 mm 24.3 mm
(0.024") (0.957")
1. Metric Dimensions Govern–English are in parentheses for reference only.
2. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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