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74VCXH16240DT(2000) View Datasheet(PDF) - ON Semiconductor

Part Name
Description
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74VCXH16240DT
(Rev.:2000)
ON-Semiconductor
ON Semiconductor ON-Semiconductor
74VCXH16240DT Datasheet PDF : 12 Pages
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74VCXH16240
Low-Voltage 1.8/2.5/3.3V
16-Bit Buffer
With 3.6 V–Tolerant Inputs and Outputs
(3–State, Inverting)
The 74VCXH16240 is an advanced performance, inverting 16–bit
buffer. It is designed for very high–speed, very low–power operation
http://onsemi.com
in 1.8 V, 2.5 V or 3.3 V systems.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
MARKING DIAGRAM
48
to 3.3 V busses. It is guaranteed to be over–voltage tolerant to 3.6 V.
The 74VCXH16240 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16–bit operation. The 3–state outputs are
48
1
74VCXH16240DT
AWLYYWW
controlled by an Output Enable (OEn) input for each nibble. When
TSSOP–48
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state. The data inputs include active bushold
DT SUFFIX
CASE 1201
1
circuitry, eliminating the need for external pull–up resistors to hold
unused or floating inputs at a valid logic state.
A = Assembly Location
Designed for Low Voltage Operation: VCC = 1.65–3.6 V
3.6 V Tolerant Inputs and Outputs
WL = Wafer Lot
YY = Year
WW = Work Week
High Speed Operation: 2.5 ns max for 3.0 to 3.6 V
3.0 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
Static Drive: ±24 mA Drive at 3.0 V
ORDERING INFORMATION
±18 mA Drive at 2.3 V
Device
Package Shipping
±6 mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
74VCXH16240DT
74VCXH16240DTR
TSSOP
TSSOP
39 / Rail
2500 / Reel
Logic State
IOFF Specification Guarantees High Impedance When VCC = 0 V
Near Zero Static Supply Current in All Three Logic States (20 µA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds ±300mA @ 125°C
ESD Performance: Human Body Model >2000 V; Machine Model >200 V
†NOTE: To ensure the outputs activate in the 3–state condition, the output
enable pins should be connected to VCC through a pull–up resistor. The
value of the resistor is determined by the current sinking capability of the
output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2000
1
August, 2000 – Rev. 0
Publication Order Number:
74VCXH16240/D
 

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