datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

74VHC132M View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
74VHC132M QUAD 2-INPUT SCHMITT NAND GATE ST-Microelectronics
STMicroelectronics ST-Microelectronics
74VHC132M Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
®
74VHC132
QUAD 2-INPUT SCHMITT NAND GATE
s HIGH SPEED: tPD = 4.9 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s TYPICAL HYSTERESIS: Vh = 1V at VCC = 4.5V
s POWER DOWN PROTECTION ON INPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.8V (Max.)
DESCRIPTION
The 74VHC132 is an advanced high-speed
CMOS QUAD 2-INPUT SCHMITT NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
PRELIMINARY DATA
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHC132M
74VHC132T
regard to the supply voltage. This device can be
used to interface 5V to 3V.
Pin configuration and function are the same as
those of the VHC00 but the VHC132 has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
1/7
Direct download click here
 

Share Link : ST-Microelectronics
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]