74VCX162373(2004) View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
View to exact match
74VCX162373
(Rev.:2004)
(Rev.:2004)
Fairchild Semiconductor
74VCX162373 Datasheet PDF : 8 Pages
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Connection Diagram
Truth Tables
Inputs
Outputs
LE1
OE1
I0–I7
O0–O7
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
Inputs
Outputs
LE2
OE2
I8–I15
O8–O15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW of Latch Enable
Functional Description
The 74VCX162373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the In enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
Logic Diagram
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LEn. The
3-STATE outputs are controlled by the Output Enable
(OEn) input. When OEn is LOW the standard outputs are in
the 2-state mode. When OEn is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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