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74LVX174 View Datasheet(PDF) - STMicroelectronics

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74LVX174 Datasheet PDF : 12 Pages
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74LVX174
LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR
WITH 5V TOLERANT INPUTS
s HIGH SPEED:
fMAX = 180MHz (TYP.) at VCC = 3.3V
s 5V TOLERANT INPUTS
s INPUT VOLTAGE LEVEL:
VIL=0.8V, VIH=2V at VCC=3V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
s IMPROVED LATCH-UP IMMUNITY
s POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVX174MTR
74LVX174TTR
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 3
1/12
 

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