74LVX138 View Datasheet(PDF) - STMicroelectronics

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74LVX138

LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.) WITH 5V TOLERANT INPUTS

STMicroelectronics 

74LVX138

LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.)

WITH 5V TOLERANT INPUTS

s HIGH SPEED:

tPD = 5.5ns (TYP.) at VCC = 3.3V

s 5V TOLERANT INPUTS

s INPUT VOLTAGE LEVEL:

VIL=0.8V, VIH=2V at VCC=3V

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s LOW NOISE:

VOLP = 0.3V (TYP.) at VCC = 3.3V

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 4mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 138

s IMPROVED LATCH-UP IMMUNITY

s POWER DOWN PROTECTION ON INPUTS

DESCRIPTION

The 74LVX138 is a low voltage CMOS 3 TO 8

LINE DECODER (INVERTING) fabricated with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology. It is ideal for low

power, battery operated and low noise 3.3V

applications.

If the device is enabled, 3 binary select (A, B, and

C) determine which one of the outputs will go low.

If enable input G1 is held low or either G2A or G2B

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

T&R

74LVX138MTR

74LVX138TTR

is held high, the decoding function is inhibited and

all the 8 outputs go to high.

Tree enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

This device can be used to interface 5V to 3V

system. It combines high speed performance with

the true CMOS low power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Figure 1: Pin Connection And IEC Logic Symbols

August 2004

Rev. 3

1/12

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