datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

74LVT240MTC View Datasheet(PDF) - Fairchild Semiconductor

Part Name
Description
View to exact match
74LVT240MTC Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Physical Dimensions
20
B
13.00
12.60
11.43
A
11
10.65 7.60
10.00 7.40
9.50
2.25
1
PIN ONE
INDICATOR
0.51
0.35
10
1.27
0.25 M C B A
0.65
1.27
LAND PATTERN RECOMMENDATION
2.65 MAX
SEE DETAIL A
(R0.10)
(R0.10)
8°
0°
1.27
0.40
(1.40)
0.75
0.25
X
45°
0.33
C
0.20
0.30
0.10
0.10 C
SEATING PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE PLANE
0.25
SEATING PLANE
DETAIL A
SCALE: 2:1
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) CONFORMS TO ASME Y14.5M-1994
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
F) DRAWING FILENAME: MKT-M20BREV3
Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1999 Fairchild Semiconductor Corporation
74LVT240, 74LVTH240 Rev. 1.5.0
6
www.fairchildsemi.com
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]