74LVT16373MTD View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
View to exact match
74LVT16373MTD Datasheet PDF : 8 Pages
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Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
Description
OEn
LEn
I0–I15
O0–O15
NC
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
3-STATE Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
O0
NC OE1 LE1 NC
I0
B
O2
O1
NC NC
I1
I2
C
O4
O3
VCC VCC
I3
I4
D
O6
O5 GND GND I5
I6
E
O8
O7 GND GND I7
I8
F
O10
O9 GND GND
I9
I10
G
O12
O11 VCC VCC
I11
I12
H
O14
O13
NC
NC
I13
I14
J
O15 NC OE2 LE2 NC
I15
Truth Tables
Inputs
Outputs
LE1
OE1
X
H
H
L
H
L
L
L
I0–I7
X
L
H
X
O0–O7
Z
L
H
Oo
Inputs
Outputs
LE2
OE2
I8–I15
O8–O15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
Oo
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z HIGH Impedance
Oo Previous output prior to HIGH-to-LOW transition of LE
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