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74LVT374PWDH View Datasheet(PDF) - Philips Electronics

Part Name74LVT374PWDH Philips
Philips Electronics Philips
Description3.3V Octal D-type flip-flop; positive-edge trigger (3-State)
74LVT374PWDH Datasheet PDF : 12 Pages
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Philips Semiconductors
3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74LVT374
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
1
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
SA00111
FUNCTION TABLE
INPUTS
OE
CP
Dn
INTERNAL
REGISTER
OUTPUTS
Q0 – Q7
L
l
L
L
L
h
H
H
L
X
NC
NC
H
X
X
NC
Z
H=
h=
L=
l=
NC=
X=
Z=
=
=
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
not a Low-to-High clock transition
LOGIC DIAGRAM
D0
D1
D2
D3
D4
3
4
7
8
13
1
EN
11
C1
3
1D
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
SA00112
OPERATING MODE
Load and read register
Hold
Disable outputs
D5
14
D6
17
D7
18
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
11
CP
1
OE
2
5
6
9
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SA00113
1998 Feb 19
3
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DESCRIPTION
The 74LVT374 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
The 74LVT374 is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates.

FEATURES
• Inputs and outputs on opposite side of package allow easy interface to microprocessors
• 3-State outputs for bus interfacing
• Common output enable
• TTL input and output switching levels
• Input and output interface capability to systems at 5V supply
• Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Live insertion/extraction permitted
• No bus current loading when output is tied to 5V bus
• Power-up 3-State
• Power-up reset
• Latch-up protection exceeds 500mA per JEDEC Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model

 

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