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74LVQ373 데이터 시트보기 (PDF) - Fairchild Semiconductor

부품명74LVQ373 Fairchild
Fairchild Semiconductor Fairchild
상세내역Low Voltage Octal Transparent Latch with 3-STATE Outputs
74LVQ373 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
(ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source or
Sink Current
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC + 0.5V
20 mA
+20 mA
0.5V to VCC + 0.5V
±50 mA
±400 mA
65°C to +150°C
±300 mA
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
VIN from 0.8V to 2.0V
VCC @ 3.0V
2.0V to 3.6V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
Note 1: The Absolute Maximum Ratingsare those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditionstable will define the conditions
for actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C Units
(V)
Typ
Guaranteed Limits
Conditions
VIH
Minimum High Level
Input Voltage
VIL
Maximum Low Level
Input Voltage
VOH
Minimum High Level
Output Voltage
VOL
Maximum Low Level
Output Voltage
IIN
Maximum Input
Leakage Current
3.0
1.5
2.0
3.0
1.5
0.8
3.0
2.99
2.9
3.0
2.58
3.0
0.002
0.1
3.0
0.36
3.6
±0.1
2.0
0.8
2.9
2.48
0.1
0.44
±1.0
V
VOUT = 0.1V
or VCC 0.1V
V
VOUT = 0.1V
or VCC 0.1V
V
IOUT = −50 µA
V
VIN = VIL or VIH (Note 3)
IOH = −12 mA
V
IOUT = 50 µA
V
VIN = VIL or VIH (Note 3)
IOL = 12 mA
µA
VI = VCC,
GND
IOLD
Minimum Dynamic
3.6
IOHD
Output Current (Note 4)
3.6
ICC
Maximum Quiescent
3.6
Supply Current
36
mA VOLD = 0.8V Max (Note 5)
25
mA VOHD = 2.0V Min (Note 5)
4.0
40.0
µA
VIN = VCC
or GND
IOZ
Maximum 3-STATE
Leakage Current
3.6
±0.25
±2.5
VOLP
VOLV
VIHD
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Maximum High Level
Dynamic Input Voltage
3.3
0.4
0.8
3.3
0.3
0.8
3.3
1.7
2.0
VI (OE) = VIL, VIH
µA
VI = VCC, GND
VO = VCC, GND
V
(Note 6)(Note 7)
V
(Note 6)(Note 7)
V
(Note 6)(Note 8)
VILD
Maximum Low Level
Dynamic Input Voltage
3.3
1.6
0.8
V
(Note 6)(Note 8)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75for commercial temperature range is guaranteed.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f = 1 MHz.
3
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General Description
The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

Features
■ Ideal for low power/low noise 3.3V applications
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ and QSOP packages
■ Guaranteed simultaneous switching noise level and
   dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity

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